Overview
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed-
signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications.
Learn more about Single-Protocol PHY IP core
Model authoring kits (MAKs) enable the rapid development of transaction-level models, TLMs, of a given functionality or protocol. MAKs include base functionalities that are common to all models independent of the RTL implementation in a well-structured way, allowing for maximum reuse. The DesignWare System-Level Library provides MAKs for UART and USB. Taking the example of a USB 2.0 EHCI controller model using MAKs, this paper explains the significant design time reduction that can be achieved.
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability and schedule. Packaged as a complete, integrated place-and
Discover Synopsys’ first complete UFS 5.0 and M‑PHY v6.0 IP solution for high-speed, efficient storage in mobile, automotive, and AI-enabled systems.
Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
