Vendor: Synopsys, Inc. Category: Single-Protocol PHY

USB 2.0 picoPHY in TSMC (40nm, 28nm)

The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…

USB 2.0 TSMC 28nm Available on request View all specifications

Overview

The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applications such as next—generation, feature-rich smartphones, netbooks, and mobile internet devices. For reduced silicon cost and longer battery life, the Synopsys USB 2.0 picoPHY IP delivers smaller die area and lower leakage power compared to current USB 2.0 PHY IP products. Optimized for mobile and consumer electronic applications, the Synopsys USB 2.0 picoPHY implements the latest Battery Charger version 1.1 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF). Architected for the industry’s most advanced process technologies, the USB 2.0 picoPHY is designed with features created to minimize effects due to variations in foundry process, device models, package and board parasitics. The Synopsys USB 2.0 picoPHY builds on years of customer success with Synopsys’ silicon-proven USB 2.0 PHY IP product line, which has been ported to over 50 process node and configuration combinations ranging from 180nm to 28nm. When combined with the Synopsys Host, Device or On-The-Go (OTG) digital controllers and verification IP, the Synopsys USB 2.0 picoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.

Key features

  • Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
  • Small PHY macro area
  • Low power
  • Advanced power management features, including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
  • OTG 2.0 support including Attach Detection Protocol (ADP)
  • Supports all OTG features, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Battery Charger v1.1 support, including the latest Accessory Charger Adapter (ACA) functionality Enhanced test capabilities includes added CDR margin testing, automatic test packet generation, and reduced pin count test requirements via multiplexing of ID pin
  • Enhanced Reference Clock support for mobile and low-cost applications including 9.6, 10, 12, 19.2, 20, 24, and 50MHzEnhanced analog programmability for integration into low-cost packaging and PCB designs as well as external audio switch support
  • Reduced pin count with a single ground design for lower packaging costs
  • Architecture designed to minimize effects due to foundry process, chip and board parasitics, and process device model variations
  • USB 2.0 Transceiver Macrocell Interface (UTMI+ Level 3) specification (8-bit interface at 60MHz and 16-bit interface at 30MHz operation)
  • On-chip PLL reduces clock noise and eliminates external clock generator requirement
  • Support for off-chip charge pump regulator to generate 5V Vbus signals
  • Designed for minimal power dissipation for low-power and bus-powered devices
  • Suspend, resume, and remote wakeup mode support
  • USB 2.0 test mode support
  • Built-in self-test features to confirm Hi-Speed, Full-Speed, and Low-Speed operation
  • Minimal external component cost; requires one external resistor and crystal (optional)
  • Low area ESD and CUP I/O pads provided with the macro
  • Based on Synopsys’ industry leading USB Implementer’s Forum certified Hi-Speed USB 2.0 nanoPHY architecture
  • Designed for rapid integration with Synopsys’ single-port Hi-Speed USB 2.0 OTG, Device and Host Controllers
  • Supports USB Type-C and traditional USB connectors

Benefits

  • The Synopsys USB 2.0 picoPHY is designed for advanced CMOS digital logic processes
  • Integrates high-speed, mixed-signal custom CMOS circuitry designed to the UTMI+ Level 3 specification Supports the USB 2.0 480 Mbps protocol and data rate (Hi-Speed)
  • Backwards compatible with USB 1.1 operating at 1.5 Mbps (Low-Speed) and 12 Mbps (Full-Speed)
  • Can be used in USB Device, Host, or On-The-Go applications
  • Supports the USB Type-C™ connector standard

Applications

  • Digital cameras and camcorders
  • USB video products
  • Wireless routers and networking
  • Gaming
  • Storage
  • Smartphones
  • Tablets and ultrabooks
  • Set-top boxes
  • Smart TVs
  • Media players

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm Available on request

Specifications

Identity

Part Number
dwc_usb2_picophy_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 2.0

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is USB 2.0 picoPHY in TSMC (40nm, 28nm)?

USB 2.0 picoPHY in TSMC (40nm, 28nm) is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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