Vendor: M31 Technology Corp. Category: Single-Protocol PHY

USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C

M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…

USB 2.0 View all specifications

Overview

M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumption. M31 utilizes a whole new design architecture to implement the USB 2.0 IP without sacrificing the performance associated with USB 2.0. The USB 2.0 IP is not only suitable for USB peripherals, but also an optimized solution for SOCs that desire multiple USB ports.

Key features

  • Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
  • Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
  • Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
  • Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator or external clock source
  • Integrated PLL to provide a variety of stand-alone clock outputs for USB related applications

Block Diagram

USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C block diagram

Specifications

Identity

Part Number
USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C
Vendor
M31 Technology Corp.
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 2.0

Provider

Learn more about Single-Protocol PHY IP core

M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C

With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.

High-Speed PCIe and SSD Development and Challenges

PCIe stands for Peripheral Component Interconnect Express (PCIe), which is a very important specification in computer buses. It is widely used in a large number of applications for data exchange communication within computer components, such as network cards, graphics cards, and nowadays NVMe solid state drives, which are mostly connected to the motherboard via PCIe. Since its introduction in 2003, PCIe has evolved into a fifth or even sixth-generation specification.

Mastering Key Technologies to Realize the Dream - M31 IP Integration Services

Throughout the development of the industry, the evolution of advanced semiconductor manufacturing processes has led to an increase in production costs, high-speed interface bandwidth, and the difficulty and risk in IP and SoC integration. That results in a significant increase in development costs for chip manufacturers, especially in the investment of manpower, and EDA tools are becoming more challenging.

M31 on the Specification and Development of MIPI Physical Layer

MIPI is the abbreviation of "Mobile Industry Processor Interface". This article will introduce the physical layer specifications of MIPI architecture, and explain the features and benefits of D-PHY and C-PHY respectively. Then, the MIPI perspective on the development and challenges of automotive electronics and the professional MIPI technical services that M31 can provide will be shared.

Frequently asked questions about Single-Protocol PHY IP

What is USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C?

USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C is a Single-Protocol PHY IP core from M31 Technology Corp. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP