Vendor: Rambus, Inc. Category: Single-Protocol PHY

PCIe 6.2 Switch

The PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations.

PCIe Gen6 View all specifications

Overview

The PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the connection of one upstream port and multiple downstream ports as a fully configurable interface subsystem. It is backward compatible to PCIe 5.0.

How the PCIe 6.2 Switch Works

The PCIe 6.2 Switch is the first embedded switch IP available on the market architected to be physically aware.  The switch IP leverages configurable pipeline stages and a fully non-blocking multi-stage routing crossbar to enable implementation of embedded switch logic even in large chips with large physical separation between ports.

The PCIe switch IP transparently manages upstream-downstream data flow as well as peer-to-peer transfers between downstream ports, delivering the flexibility, scalability and configurability required for connecting multiple devices, including NVMe SSDs.

Key features

  • PCI Express Interfaces
    • 1 upstream port, up to 7 downstream ports
    • Up to 128 lanes
    • Up to x16 link width per port
    • Link rate of 2.5, 5, 8, 16, 32 and 64 GT/s per lane
    • Supports PCIe Base Revision 6.2
    • Supports PHY Interface for PCIe (PIPE) 6.2.1
    • Single Virtual Channel (VC) implementation
    • Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit, 128 bit)
    • Configurable Receive and Replay buffer sizes
    • Advanced Error Reporting (AER) supported on each port
    • ECRC generation and check
    • ARI supported
    • Lane reversal supported
    • Independent configuration of link width, link speed, equalization settings, and PIPE interface width per-PCIe port
    • Support for Hot Plug on every downstream port
  • Switching Logic
    • PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
    • L1 and wake-up events forwarding
    • Peer-to-Peer transactions support between downstream ports
    • Configurable Egress Buffer for non-blocking output queueing switch performance
    • Downstream Port Containment (DPC) supported
    • Round-Robin arbitration
    • Built-in advanced data protection including ECRC, LCRC, ECC and Parity
    • Test port available for switch monitoring
    • Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic
    • Physically aware switch architecture: configurable pipeline stages and fully non-blocking multi-stage routing crossbar
    • Data Bus Inversion support for EM/IR reduction of large busses
    • Manages multiple packets per clock cycle

Block Diagram

PCIe 6.2 Switch block diagram

Specifications

Identity

Part Number
PCIe 6.2 Switch
Vendor
Rambus, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen6

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Rambus, Inc.
HQ: USA

Learn more about Single-Protocol PHY IP core

Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security

On August 25, 2026, the National Security Agency (NSA) released two technical reports addressing intentional threats to application-specific integrated circuits during design and manufacturing: the “ASIC Best Practices Threat Catalog” and “Application Specific Integrated Circuit Level of Assurance 1 (LoA1) Best Practices”.

Frequently asked questions about Single-Protocol PHY IP

What is PCIe 6.2 Switch?

PCIe 6.2 Switch is a Single-Protocol PHY IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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