Xilinx provides an 100M/1G TSN Subsystem to accelerate time to market and drive the convergence of low latency deterministic Indu…
- Ethernet
High-Speed Serial IP cores enable the high-bandwidth connectivity required by modern SoCs, AI accelerators, networking equipment, storage systems, telecom infrastructure, aerospace platforms, and data center devices. These IP solutions provide reliable, standards-compliant communication between chips, boards, systems, and external networks.
This catalog includes IP cores supporting industry-standard protocols such as PCI Express, CXL, Ethernet, USB, Fibre Channel, SAS, InfiniBand, Interlaken, JESD204, Optical Transport, CPRI, RapidIO, UniPro, CoaXPress, SpaceWire, and other high-speed serial interfaces. Solutions may include PHYs, controllers, protocol stacks, subsystem IP, and verification components.
Compare high-speed serial IP offerings from multiple vendors based on supported standards, data rates, feature sets, protocol compliance, silicon efficiency, and target applications to identify the right connectivity solution for advanced ASIC and SoC designs.
Xilinx provides an 100M/1G TSN Subsystem to accelerate time to market and drive the convergence of low latency deterministic Indu…
1G/10G/25G Switching Ethernet Subsystem
The 1G and 10G Switching Ethernet Subsystem dynamically switches an Ethernet Media Access Controller (MAC) between 1G or 10G phys…
TSN Ethernet Endpoint Controller
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time …
10G UDP/IP Hardware Protocol Stack
The core Implements a UDP/IP hardware protocol stack that enables wire-speed communication over a LAN or a point-to-point connect…
1G UDP/IP Hardware Protocol Stack
The core Implements a UDP/IP hardware protocol stack that enables wire-speed communication over a LAN or a point-to-point connect…
Configuration-over-Ethernet (COE) IP Core
Configuration-over-Ethernet (COE) is a Layer 2 configuration protocol design by SoC-e to access remotely to FPGAs that implements…
UOE is high performance and customizable UDP/IP hardware stack compliant with RFC 768 (for UDP) and RFC 791 (for IPv4)/RFC 2460(f…
Serial RapidIO 2.1 Endpoint IP Core
The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, hig…
Serial RapidIO - Physical Layer Interface
The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2.
Lattice's Quad GbE Over SONET/SDH Bridge is a hard IP Core implemented in two Lattice ORCA4E06 devices that act as a bridge betwe…
PCI Express x1, x4 Root Complex Lite IP Core
PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platf…
JESD207 is a Radio Front End – Base Band Digital Parallel (RBDP) interface between a Radio Front-end integrated circuit (RFIC) an…
JEDEC Standard No.
The Ethernet Media Access Controller (MAC) core can be configured to operate in either the Gigabit mode (1000 Mbits/sec data rate…
Ethernet 1G/10G flexiMAC MACO Core
The LatticeSCM Ethernet flexiMAC™ MACO™ IP core is a flexible packet framer and parser that can implement Layer2 (data link layer…
The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
UltraScale+ Integrated 100G Ethernet Subsystem
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC), Physical Coding Sublayer (PCS),…
UltraScale+ Device Integrated Block for PCI Express (PCIe)
The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable seria…
UltraScale Integrated 100G Ethernet Subsystem
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PC…
UltraScale / UltraScale+ Interlaken
The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect proto…