Vendor: Lattice Semiconductor Corp. Category: JESD204

JESD207 IP

JESD207 is a Radio Front End – Base Band Digital Parallel (RBDP) interface between a Radio Front-end integrated circuit (RFIC) an…

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Overview

JESD207 is a Radio Front End – Base Band Digital Parallel (RBDP) interface between a Radio Front-end integrated circuit (RFIC) and a Baseband integrated circuit (BBIC). This IP core together with DDR and PLL functionality integrated in the LatticeECP3™ FPGAs implements baseband (BB) side data and control plane paths. It can be used to connect to a radio front-end (RF) transceiver device with integrated analog to digital converter (ADC) and digital to analog converter (DAC).

The Lattice JESD207 IP core is fully compliant to the JESD207 JEDEC specification.

Key features

  • Data path clock and data rate controlled by RFIC (configured by BBIC) up to 90 MHz and 180 MSps
  • Data width matched to baseband sample width – 10 or 12 bits
  • Raw data path interface transfer bandwidth up to 1.8 or 2.2 Gbps
  • Double data rate (DDR) source-synchronous data path transfer timing
  • Low latency (single baseband complex sample period) data transfer
  • Low implementation complexity

Block Diagram

JESD207 block diagram

Specifications

Identity

Part Number
JESD207
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Lattice Semiconductor Corp.

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD207 IP?

JESD207 IP is a JESD204 IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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