Vendor: Xilinx, Inc. Category: Ethernet

USXGMII Subsystem

The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with…

Overview

The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with a mechanism to carry a single port of 10M, 100M, 1G, 2.5G, 5G or 10GE over an IEEE 802.3 Clause 49 BASE-R physical coding sublayer/physical layer (PCS/PHY). The USXGMII IP core is delivered as encrypted register transfer level (RTL) through the Vivado® Design Suite targeted for Xilinx UltraScale+ and UltraScale devices.

Key features

  • Designed to meet the USXGMII specification EDCS-1467841 revision 1.4
  • Supports 10M, 100M, 1G, 2.5G, 5G, or 10GE data rates over a 10.3125 Gb/s link
  • Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included
  • Code replication/removal of lower rates onto the 10GE link
  • Rate adaption onto user clock domain
  • 32-bit AXI4-Stream interface for datapath
  • Optional AXI4-Lite register interface
  • Support for 802.3x and priority-based pause operation
  • Detailed statistics gathering
  • Support for custom preambles

Specifications

Identity

Part Number
|EF-DI-USXGMII-MAC-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Ethernet IP core

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Frequently asked questions about Ethernet IP cores

What is USXGMII Subsystem?

USXGMII Subsystem is a Ethernet IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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