Vendor: Lattice Semiconductor Corp. Category: JESD204

JESD204B IP Core

JEDEC Standard No.

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Overview

JEDEC Standard No. 204B (JESD204B) describes a serialized interface between data converters and logic devices. It contains the information necessary to allow designers to implement logic devices which can communicate with other devices (converters) that are compliant with the standard. Lattice’s JESD204B 3G/5G IP Core offerings support both an Rx core (ADC to FPGA direction) and/or a Tx core (FPGA to DAC direction). The Rx and Tx cores can each be generated separately and with different parameters.

Key features

  • Subsets of JEDEC Standard No. 204B(JESD204B.01) July 2011
  • Rx core performs lane alignment based on Subclass 0 and Subclass 1
  • Rx core performs frame alignment detection / monitoring and octet reconstruction
  • Rx core performs user-enabled descrambling
  • Rx core recovers link configuration parameters during initial lane synchronization and compares them to user selected parameters to generate a configuration mismatch error
  • Tx core performs user-enabled scrambling
  • Tx core generates initial lane alignment sequence
  • Tx core performs alignment character generation
  • Tx core sources link configuration data with user selected parameter values during initial lane synchronization Sequence
  • 16 bit(3G) or 32 bit(5G) fabric interface per channel for low core frequency
  • One-shot frame/multi-frame boundary flags with one clock ahead of data make users easy to control the transition of the state machines for framer / de-framer

Block Diagram

ECP block diagram

Specifications

Identity

Part Number
ECP
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Lattice Semiconductor Corp.

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204B IP Core?

JESD204B IP Core is a JESD204 IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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