I2C / I3C IP cores enable standards-based low-speed control and peripheral communication in modern SoC and ASIC designs.
These IP cores support low-speed serial control and sensor communication, including modern I3C enhancements for bandwidth, in-band interrupt support, and dynamic addressing, helping designers integrate interoperable control links across embedded, automotive, industrial, and connectivity-focused systems
This catalog allows you to compare I2C / I3C IP cores from leading vendors based on feature set, latency, power consumption, and process node compatibility.
Whether you are designing sensor hubs, mobile platforms, embedded controllers, or automotive electronics, you can find the right I2C / I3C IP for your application.
I2C Controller IP – Slave, Parameterized FIFO, AXI Master Interface (I2C2AXI)
The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, Parameterized FIFO, APB Master Interface (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection
The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication.
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
The DB-I3C-BASIC-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI …
The eSi-I2C core implements the I2C two-wire protocol.
The BRIDGE_UART_I2C IP Core provides a simple and convenient way to interface a standard UART bus to a standard I2C bus.
I3C Controller IP- Slave, Parameterized FIFO, APB Bus
The DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
I3C Controller IP – Master, Parameterized FIFO, APB Bus
The DB-I3C-M-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus
The DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – …
I2C Slave Serial Interface Controller
The I2C_SLAVE IP Core is a Philips® I2C compliant slave interface controller.
I2C Controller IP – Slave, Parameterized FIFO, AHB Bus
The DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 2…
I2C Controller IP – Slave, Parameterized FIFO, APB Bus
The DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP – Slave, Parameterized FIFO, AXI Bus
The DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 4…
The DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management …
I2C Controller IP – Slave, User Register Interface, No CPU Required
The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal conf…
The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applicatio…
Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device.
The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stac…
The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.