Graphics and Vision IP cores provide the hardware acceleration engines required for image processing, video analytics, visual computing, and display management in advanced SoC and ASIC designs.
This category includes GPU, ISP (Image Signal Processor), Video Processing, Display Controller, Image Conversion, and Vision Subsystem IP cores. These solutions enable functions such as graphics rendering, image enhancement, video encoding and decoding, color space conversion, display management, camera processing pipelines, and real-time computer vision acceleration.
This catalog allows semiconductor engineers to evaluate and compare Graphics and Vision IP solutions from multiple vendors based on supported video standards, image quality, AI vision capabilities, throughput, latency, power consumption, silicon area, and process node compatibility.
Whether developing automotive ADAS platforms, AI-enabled edge devices, smart cameras, industrial vision systems, AR/VR applications, mobile processors, or multimedia SoCs, engineers can identify the Graphics and Vision IP cores best suited to their performance, power, and integration requirements.
JPEG Encoder Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
The KJN-4ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
The KJN-4 conform to the JPEG baseline format for compressing/decompressing still images.
JPEG Encoder Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
The KJN-1ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 24fps@100MHz.(1sample/clk)
The KJN-1+ conform to the JPEG baseline format for compressing/decompressing still images.
The PowerVR Series7XT family pushes mobile and embedded GPU performance to new heights with configurations featuring 2 to 16 clus…
IP
2D Graphics Hardware Accelerator (AXI4 Bus)
The DB9200AXI4 2D Graphics Hardware Accelerator / Engine Verilog IP Core renders graphics frames as follows: Generates bitmaps fr…
Lossless JPEG Codec Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
KJN-1LSC conform to the Lossless JPEG format(ITU-T T.81 Annex H) and compress/decompress image data without data loss in comparis…
The PowerVR Series7XE family is a range of ultra-efficient, -featured GPUs that includes the world’s smallest Android Extension P…
Shader architecture type 3D GPU
A shader architecture type 3D GPU Integrating the OpenVG 1.1 hardware processing pipeline
Highly effective and small gate size Mosquito Noise Reducer
JVC KENWOOD's Mosquito Noise Reducer IP, which is already used in its products, is now available for licensing.
JPEG Codec 4K(YUV422) 96fps@200MHz,
The KJN-7EX conform to the JPEG baseline format/JPEG Extended DCT-based process for compressing/decompressing 8bit/12bit still im…
Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)
The DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Inte…
JVC Object-Based Gloss Enhancer
JVC's Object-Based Gloss Enhancer IP, which is already used in its products, is now available for licensing.
Gen 4 2D (vector graphics) & 3D GPU IP
A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load.
The TXT_OVERLAY IP Core is a versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RG…
BitBLT Graphics Hardware Accelerator (AXI4 Bus)
The DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comma…
BitBLT Graphics Hardware Accelerator (AHB Bus)
The DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comman…
BitBLT Graphics Hardware Accelerator (AXI Bus)
The DB9100AXI BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comman…
The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or…