Dual-core video decoder - AV1, HEVC, AVC, VP9
Dual-core video decoder - AV1, HEVC, AVC, VP9
- AV1 + 2
Graphics and Vision IP cores provide the hardware acceleration engines required for image processing, video analytics, visual computing, and display management in advanced SoC and ASIC designs.
This category includes GPU, ISP (Image Signal Processor), Video Processing, Display Controller, Image Conversion, and Vision Subsystem IP cores. These solutions enable functions such as graphics rendering, image enhancement, video encoding and decoding, color space conversion, display management, camera processing pipelines, and real-time computer vision acceleration.
This catalog allows semiconductor engineers to evaluate and compare Graphics and Vision IP solutions from multiple vendors based on supported video standards, image quality, AI vision capabilities, throughput, latency, power consumption, silicon area, and process node compatibility.
Whether developing automotive ADAS platforms, AI-enabled edge devices, smart cameras, industrial vision systems, AR/VR applications, mobile processors, or multimedia SoCs, engineers can identify the Graphics and Vision IP cores best suited to their performance, power, and integration requirements.
Dual-core video decoder - AV1, HEVC, AVC, VP9
Dual-core video decoder - AV1, HEVC, AVC, VP9
Single-core video codec - HEVC, AVC
Single-core video codec - HEVC, AVC
"Image Signal Processor" with the minimum functions required for image processing system
Because our ISP-IP is equipped with the minimum necessary functions, it reduces the load on the CPU that performs some solutions …
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single channel ADAS chip with FuSa monitor
The SFA250A is aimed at Functional Safety (FuSa) applications such as Driver Assistance Systems (ADAS) and contains an independen…
This IP reference platform has been architected with ISO26262 applications and the fast integration of customer IP in mind from t…
H.264/265 Video Encoder and Decoder IP
The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a flexible architecture targeting at le…
JPEG Encoder 8K (YUV422) 96fps@200MHz. (32Sample/clk)
The KJN-9EX_ENC consists of IP cores that conform to the JPEG Extended DCT-based process for compressing 8bit/12bit still images.
JPEG Encoder Full HD(YUV422) 30fps@126MHz(1Sample/clk)
The KJN-F1ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 30fps@126MHz(1Sample/clk)
The KJN-F1 conform to the JPEG baseline format for compressing/decompressing still images.
HDR improves the visibility of the output image compared to the input images by increasing the contrast of the image/video reprod…
Color Gamut controls the color of the output image/video compared to the input image/video for high color reproduction on the dis…
The Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue.
Single-core video encoder - HEVC, AVC
Single-core video encoder - HEVC, AVC
BTREE’s MSCALE enlarges the input video to fit the panel size.
BTREE’s BSCALE enlarges or reduces the input video to fit the panel size.
Video Encoder IP optimized for HD use cases
The E100 Series of Encoder IP enables HD/1080P60 resolution encoding up to 5MPixels in a single core.
Single-core video codec - HEVC, AVC
Single-core video codec - HEVC, AVC
Single-core video decoder - AV1, HEVC, AVC, VP9, AVS2
Single-core video decoder - AV1, HEVC, AVC, VP9, AVS2