PHY and SerDes IP cores are essential building blocks for high-speed data transmission in modern semiconductor designs. This category includes physical layer IP and serializer/deserializer solutions used to implement reliable chip-to-chip, die-to-die, backplane and interface connectivity across networking, compute, storage, automotive and consumer applications.
Browse PHY / SerDes semiconductor IP for high-speed interfaces requiring robust signal integrity, scalable lane configurations, low power and standards-oriented interoperability. Compare controller-adjacent PHY IP, generic SerDes architectures and specialized high-speed connectivity solutions from multiple vendors for integration into ASICs, SoCs and advanced package designs.
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC
Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver f…
MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-…
MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specific…
MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
The MIPI D-PHY Analog RX IP Core completely complies with the D-PHY specification, version 1.2.
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP
An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX …
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP
The Display Port 1.4 Rx IP Channel's maximum capacity is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
USB 2.0 PHY IP, Silicon Proven in UMC 28HPC
The USB 2.0 PHY IP Core offers a physical layer (PHY) solution for high performance and low power.
USB 2.0 PHY IP, Silicon Proven in UMC 40LP
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for excellent performance and low power consumption.
USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification with support…
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
It supports both USB 3.1 Gen1 and Gen2 with this PHY IP.
USB 3.0 PHY IP, Silicon Proven in UMC 40SP
A Universal Serial Bus (USB) transceiver is available for peripheral devices.
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 40LP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics.
PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
With compliance for PIPE 4.4 interface spec, Peripheral Component Interconnect Express (PCIe) Gen4 PHY IP complies with PCIe 4.0 …
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface sta…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface sta…
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC
The capacity of the Display Port 1.4 Rx IP Channel is supported.
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC
The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption.