IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
T2M GmbH
Category:
MIPI PHY
MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specific…
Overview
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification are all supported by the MIPI M-PHY Gear 3 IP. a high-bandwidth serial interface technology that can support HS Gear3 rates of up to 5.8Gbps and was specifically created for mobile applications to achieve reduced pin count and excellent battery efficiency. The UniPro controller and UFS Controller are supported by the RMMI interface-compliant MIPI M-PHY Gear 3 IP. The MIPI M-PHY offers reliable embedded system debugging and receiver ocular data monitoring using low-cost Build-In-Self-Test (BIST).
Key features
- Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
- Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
- Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
- Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
- Support RMMI interface for Type-I application
- Receiver eye open for monitoring and debugging
- Support Build-In-Self Test(BIST) for low-cost CP/FT
- Silicon Proven in UMC 40LP
Block Diagram
MIPI M-PHY v3.1 IP in UMC 40LP block diagram
Benefits
- 2-tap DFE, CTLE, 2-tap FFE
- Channel Loss: >14dB @6GHz Nyquist
- Low HS-Gear4 operation current and low standby current
- Competitive IP PPA leading in the market
What’s Included?
- Application Note / User Manual
- Behaviour model, and protected RTL codes
- Protected Post layout netlist and Standard Delay Format (SDF)
- Library (LIB)
- Frame view (LEF)
- Metal GDS (GDSII)
- Test patterns and Test Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 40nm | LP | In Production |
Specifications
Identity
Part Number
MIPI M-PHY v3.1 IP in UMC 40LP
Vendor
T2M GmbH
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI M-PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
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Frequently asked questions about MIPI PHY IP
What is MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP?
MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP is a MIPI PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.