PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3 SERDES PHY on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
ONFI 3.0 Compatible I/O Buffer on TSMC CLN28HPL
The ONFI 3.0 compatible I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demande…
Multi Rail LDO for SERDES on TSMC CLN3P-CLN3X
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Multi Rail LDO for SERDES on TSMC CLN3E
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Multi Rail LDO for SERDES on TSMC CLN2P
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Low Power PLL on TSMC CLN90G-GT-LP
The low-power wide range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
Low Power PLL on TSMC CLN40LP-ULP
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe Gen3 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe Gen3 PHY on TSMC CLN12FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power FracN/SSCG PLL on TSMC CLN6FF
The low power Fractional-N SSCG PLL addresses power sensitive designs required for IOT, mobile and other low power applications n…
Low Power Frac-N on TSMC CLN28HPC+
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN28HPC
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.