Vendor: Analog Bits Inc. Category: PLL

PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF

The PCIe Gen5 REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex…

TSMC 7nm N7FF View all specifications

Overview

The PCIe Gen5 REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Gen5 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments.

The PLL macro is implemented in Analog Bits’proprietary architecture that uses core and 1.8V IO devices.

With all components integrated, jitter performance and standby-power are significantly improved.

SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 24 25 38.4 MHz Input Frequency in Bypass Mode fBYPASS 100 MHz VCO Frequency FVCO 4800 MHz Output Frequency FOUT 5 100 2400 MHz Output Duty Cycle tDO 48 52 % Lock Time tLOCK 10 µs Reset Time tRESET 1 µs PLLOUT Random Filtered Phase Jitter RJPO,FILT 0.081 ps-RMS PLLOUT Random unfiltered Phase Jitter RJPO 1.03 ps-RMS Modulation Frequency FM 30 33 kHz Modulation Depth (down-spread) DMD -5000 0 ppm Area A 0.086 sq. mm Total Power IDD 12 20 mW Output Load CL 100 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: SSCG PLL Operational Range

Key features

  • High performance design emphasis for meeting low jitter requirements in PCIe Gen4 & Gen5 applications
  • Implemented with Analog Bits’ proprietary LC architecture
  • Low power consumption
  • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • Excellent jitter performance with optimized noise rejection
  • Calibration code and Bandgap voltage observability (for debug)
  • Requires no additional on-chip components or band-gaps, minimizing power consumption

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7FF —

Specifications

Identity

Part Number
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

Analog Bits to Participate in a Customer Test Chip Tapeout on TSMC A14 and Present Papers with Cerebras, Arm and Socionext on Real-Time On-Chip Power Sensing and Delivery at 2026 TSMC Global OIP Ecosystem Events

At TSMC 2026 North America OIP Ecosystem Forum, Analog Bits will showcase new real-time power observability and sensing analog IP in TSMC’s N2P process technology and present a paper with Cerebras; Papers planned with partners at global OIP Ecosystem events to highlight smarter power delivery for scalable SoCs targeting data centers, automotive and more.

Frequently asked questions about PLL IP cores

What is PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF?

PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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