Vendor: Analog Bits Inc. Category: PLL

PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC

The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…

TSMC 12nm FFC View all specifications

Overview

The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments.

The SSCG PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. Eliminating band-gaps and integrating all on-chip components such as capacitors helps the jitter performance significantly and reduces stand-by power.

SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 25 100 MHz Output Frequency FOUT 47 1500 MHz Output Duty Cycle tDO 45 55 % Lock Time tLOCK 100 µs Reset Time tRESET 1 µs PLLOUT Output Random Jitter RJO 1 ps-RMS Modulation Frequency FM 30 33 kHz Modulation Depth (down-spread) DMD -0.5 0 % Modulation Depth (center-spread) DMC -0.25 0.25 % Modulation Frequency Slew (see NOTE3) FS 1250 ppm/µs Area (drawn) A 0.091 sq. mm Total Power (unloaded) IDD 16 mW Operational Voltage (Digital) VDIG 0.72 0.8 0.88 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: SSCG PLL Operational Range SSCG PLL Functional Specification The phase-locked loop (PLL) block is provided as a drop-in functional block. The PLL accepts input frequencies of 25MHz or 100MHz, and can produce a wide range of output frequencies, as detailed in Table 1.

Key features

  • High performance design emphasis for meeting low jitter requirements in PCI Express applications
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC —

Specifications

Identity

Part Number
PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

Analog Bits to Participate in a Customer Test Chip Tapeout on TSMC A14 and Present Papers with Cerebras, Arm and Socionext on Real-Time On-Chip Power Sensing and Delivery at 2026 TSMC Global OIP Ecosystem Events

At TSMC 2026 North America OIP Ecosystem Forum, Analog Bits will showcase new real-time power observability and sensing analog IP in TSMC’s N2P process technology and present a paper with Cerebras; Papers planned with partners at global OIP Ecosystem events to highlight smarter power delivery for scalable SoCs targeting data centers, automotive and more.

Frequently asked questions about PLL IP cores

What is PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC?

PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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