Low frequency 32-kHz RC oscillator optimized for low power
Ultra-low power 32 kHz RC oscillator designed in TSMC 40 LP for IoT SoC and ULP MCU applications requiring fast wake-up.
- TSMC
- 40nm
- LP eFlash
- In Production
Clocking and timing IP cores are fundamental to semiconductor designs that require accurate clock generation, distribution, synchronization, and timing control. This category includes PLLs, DLLs, oscillators, and clock generators used in SoCs, ASICs, SerDes subsystems, processors, memory interfaces, and communication devices.
Browse clocking and timing IP from multiple vendors to compare jitter, frequency range, locking behavior, power consumption, programmability, and process support. Semi IP Hub helps chip architects and design engineers identify the right timing IP for high-performance and low-power silicon platforms.
Low frequency 32-kHz RC oscillator optimized for low power
Ultra-low power 32 kHz RC oscillator designed in TSMC 40 LP for IoT SoC and ULP MCU applications requiring fast wake-up.
Ultra-low power 32 kHz RC oscillator in TSMC 40 ULP eFlash
Ultra-low power 32 kHz RC oscillator designed in TSMC 40 ULP eFlash for IoT SoC and ULP MCU applications requiring fast wake-up.
Ultra low-power crystal-based 32 kHz clock generator
The qOSC-XTAL-LP-32k-co.05 32 kHz crystal oscillator is an excellent choice for IoT SoC designed in TSMC 40nm ULP technology with…
This IP is a phase locked loop which base on TSMC 40nm.
The OT3122t130 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for …
Ultra-Low Power Fractional PLL IP in in TSMC (12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
Low Power Fractional PLL is a general purpose frequency synthesizer with an input reference frequency range from 10 to 240 MHz an…
Low Power Fractional PLL IP in TSMC(12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
M31 LPFPLL is a low-power programmable fractional-N (LPF), phase-locked loop (PLL) for frequency synthesis.
Low Power PLL for TSMC 40nm ULP
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is design…
24-bit Cap-less ADC PLL-less 2 channels
The sADC-H1-LR.02 is a mixed (analog and digital) Virtual Component containing 2 mono ADCs, and additional functions offering an …
1.8V Programmable 100MHz Oscillator Staggered I/O Pad Set
The 1.8V 100MHz Oscillators library includes a programmable oscillator macro I/O cell.
3.3V 100MHz Oscillator I/O Pad Set
The 3.3V 100MHz Oscillators library includes a programmable oscillator macro I/O cell.
Low frequency XTAL oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of clocks.
Low frequency XTAL oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of clocks.
Low frequency 32-kHz RC oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of voltage regulators and clocks.
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
Dolphin Design offer a Reusable Power Kit Library, toward three objectives: To standardize and ease Power Management Network inte…
Low frequency XTAL oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of clocks.
Low frequency 32-kHz RC oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of voltage regulators and clocks.
Linear Regulator, Low-noise optimized for sensitive application such as RF or PLL blocks
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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily ret…