What is Low Power PLL for TSMC 40nm ULP?
Low Power PLL for TSMC 40nm ULP is a PLL IP core from Obsidian Technology listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
Obsidian Technology
Category:
PLL
Low Power PLL for TSMC 40nm ULP
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is design…
Overview
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is designed for TSMC 40nm, ULP CMOS processes.
Key features
- Wide range M, P, and N integer dividers.
- 40MHz – 600MHz output frequency range.
- Input frequency range 1.4MHz – 32MHz.
- 15pS RMS cycle to cycle jitter.
- Lock-detect function.
- Optional bypass function.
- Level shifted IO.
- Well-defined, fast startup behavior.
- -40°C to 125°C temperature operation.
- Small area: 0.03mm2 in 40nm CMOS.
- 100µW typical power dissipation.
- 0.82-1.1V digital and analog supplies.
- Silicon proven.
Block Diagram
OT3135 block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | ULP eFlash | Silicon Proven |
Specifications
Identity
Part Number
OT3135
Vendor
Obsidian Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Frequently asked questions about PLL IP cores
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.