Vendor: Obsidian Technology Category: PLL

PLL for TSMC 130nm LP

The OT3122t130 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for …

Contact Provider Request Datasheet
TSMC 130nm LP View all specifications

Overview

The OT3122t130 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the TSMC 0.13µ LP or GP CMOS processes. The design features an advanced multi-stage balanced VCO for exceptional cycle to cycle jitter performance.

This function is also available for TSMC, SMIC, IBM and ams 180nm.

Key features

  • Wide range N, M, P integer dividers.
  • 40MHz – 600MHz output frequency range.
  • Comparable frequency range 8MHz – 50MHz.
  • 18pS RMS cycle to cycle jitter at 400MHz.
  • Lock-detect function.
  • Bypass function.
  • Well defined startup behavior.
  • -40°C to 125°C temperature operation.
  • Small cell area: 0.022mm2 in 0.13µ CMOS.
  • 2mW typical power dissipation.
  • 1.8V digital and analog supplies.
  • 0.13µ CMOS process compatibility.
  • Only core voltage transistors are used in the design.
  • Silicon proven architecture.

Block Diagram

OT3122t130 block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 130nm LP —

Specifications

Identity

Part Number
OT3122t130
Vendor
Obsidian Technology
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Obsidian Technology

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is PLL for TSMC 130nm LP?

PLL for TSMC 130nm LP is a PLL IP core from Obsidian Technology listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP