Learn more about Clock Generator IP core
Using pulsed latches instead of flip-flops is a solution that has been thoroughly studied for its advantages in speed, density, and power consumption reduction [1] [2]. Even so, this solution has not been widely adopted by standard cell library providers because of the difficulties related to timing verifications: pulse width integrity and hold time closure. There is also a lack of EDA tools natively supporting this feature. Dolphin Integration delivers standard cell libraries based on pulsed latches (SESAME uHD libraries) that can be used in standard design flows and fully compatible with the most common EDA tools.
This Position Paper describes a family of Power Management IP solutions integrated by Dolphin Integration’s customers into their SoC to drastically improve Energy Efficiency (EE). SoC performance metric is changing, moving from pure performance metric (GHz or MIPS) to performance efficiency and minimum power consumption. This new metric, already crucial for IoT or mobile devices, is becoming key in various applications, like automotive, embedded or space.
Developing and verifying a control network in a low-power SoC is a challenging task, especially managing the different states of regulators and modes of power domains.
This article first describes state-of-the-art approaches to addressing this issue, and then delves into the solution promoted by Dolphin Integration to go further, thanks to the easy and secure Maestro� solution to manage SoC power mode transitions.
The virtual validation of subsystem performances (Pop-up Noise, Signal-to-Noise Ratio, Power supply Noise, Power consumption...) requires the modeling and simulation of complete subsystems. Application Hardware Modeling (AHM) consists in addressing the risks of performance degradation while integrating a Silicon IP in its Integrated Circuit (IC) and this IC on its Printed Circuit Board (PCB). The selection of relevant models for a subsystem performance, along with the creation and validation of models through equivalence checking, are the basics of Application Hardware Modeling for right-on-first-pass subsystems!
Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use.
Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The objective of this paper is dual. The first objective is to demonstrate that the « cell-by-cell » approach to compare libraries is inconsistent with actual performances results obtained after P&R of libraries on a logic circuit. The second objective is to present benchmarks and methods to compare efficiently and reliably different libraries with different architectures (e.g. CCSL versus RCSL).
