Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
CPU
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructi…
Overview
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, “B” bit manipulation, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. D45 equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its ”B” extensions provide some combination of code size reduction, performance improvement, and energy reduction, and “FD” extensions support IEEE754-compliance single and double precision floating point instructions. D45 incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. Other features include ECC for memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, PowerBrake and WFI for power management.
Key Features and Performance
AndeStar™ V5 Architecture
| Key Features | Benefits |
|---|---|
| RISC-V RV32GCPB ISA |
|
| Andes Custom Extension™ (ACE) option to create custom instructions for software acceleration |
|
| Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
| 16/32-bit mixable instruction format | For compact code density |
| 32 general-purpose registers | For better code size and performance |
| Machine (M), User (U) and Supervisor (S) Privilege levels | For Linux and advanced operating systems with protection between kernel and user programs |
CPU Core
| Key Features | Benefits |
|---|---|
| 5.67 Coremark/MHz, 2.86 DMIPS/MHz* | Excellent performance-per-MHz |
| 8-stage dual-issue in-order pipeline | Superior performance-efficiency, while allowing for high speeds |
|
Extensive branch predication features
|
|
| Physical Memory Protection (PMP), configurable up to 32 regions | Basic read/write/execute memory protection with minimum cost |
| Programmable Physical Memory Attribute (PMA), configurable up to 16 regions |
Configurable memory attributes:
|
| Performance monitors | Program code performance tuning |
|
Multiplier options
|
Option to choose between speed and area according to application's requirements |
| PowerBrake technology | Performance throttling to digitally reduce power consumption |
| StackSafe™ hardware stack protection |
|
| QuickNap™ technology | Fast power-down/wake-up support for caches |
* BSP v5.1.0, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
| Key Features | Benefits |
|---|---|
|
I-Cache & D-Cache
|
|
|
ILM & DLM
|
|
| MemBoost | Optimize cache reads and writes to achieve higher bandwidth and lower latency |
| Soft-error protection: parity for I-Cache, and ECC for D-Cache, ILM and DLM | Code and data integrity protection |
| Bus master port: AXI with 64/128-bit data, I/D joint or separate bus | User-selectable bus interface for optimal efficiency |
| Bus save port: AXI with 64/128-bit data, for ILM/DLM accesses | Efficient data transfer between CPU and SoC masters |
| Core/bus clock ratio of N:1 | Simplified SoC integration |
| 64-bit AXI Peripheral Port Interface | For latecny-sensitve peripheral |
Platform-Level Interrupt Controller (PLIC)
| Key Features | Benefits |
|---|---|
|
Implements RISC-V PLIC specification
|
Allow individual interrupts to be serviced and prioritized without sharing |
|
Enhanced interrupt features
|
|
Debug Support
| Key Features | Benefits |
|---|---|
| Implements RISC-V debug specifications ver 0.13 | Supported by industry debug tool suppliers |
| JTAG Debug Port | Industry-standard support |
| Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
| Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
Trace Support
| Key Features | Benefits |
|---|---|
| Implements RISC-V Trace 1.0 Instruction Trace interface | Supported by Andes tools |
Performance
| Core, Process | D45, 7nm |
|---|---|
| Frequency (MHz) | 1600 |
| Dynamic power (uW/MHz) | 12.1 |
| Area (mm2) | 0.036 |
TSMC 7nm FIN FET ULVT/LVT/SVT, cell height 240nm, High Speed L1 Cache Memory Compiler. Frequency condition: worst: : SSGNP/0.675V/-40oc, typical: TT/0.75v/+85oc. Power and area : typical corner. Configurations: 256-entry BTB, PMP&PMA 16-entry, 32KB I/D$ (no Local Memory), MemBoost, no FPU, with I/O constraint; die area and power are core only, 65% utilization
Key features
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V RV32 GCBP little endian:
- RV-GC: Integer, single/double precision floating point and 16-bit extensions
- RV-B Bit manipulation extensions
- RV-P (draft) DSP/SIMD extensions
- Andes V5 performance/code size extensions
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
- Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
- MemBoost for heavy memory transactions
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
Block Diagram
D45 block diagram
Applications
- Networking and Communications
- ADAS
- Video and Image Processing
- Advanced Industry Controller
- Smart wireless switch/router
Specifications
Identity
Part Number
D45
Vendor
Andes Technology Corp.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
Learn more about CPU IP core
Adding RISC-V CPU Custom Extensions Can Boost Performance, Reduce Power, and Cut Cost in 5G, AI. AR/VR, and IoT applications
By Andes
Building security into an AI SoC using CPU features with extensions
With the rapid deployment of artificial intelligence (AI), the focus of AI system on chip (SoC) design has been on building smarter, faster and cheaper
When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives
I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also RISC-V’s biggest tailwind yet.
AndeSentry – Andes’ Security Platform
Security has become a critical requirement across a wide range of applications, including mobile devices, automotive infotainment systems, and embedded platforms such as robotics. These systems must deliver robust security functionality with minimal performance overhead, which in turn requires tight and seamless integration between hardware and software to achieve optimal efficiency.
How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
Unlike fixed-ISA alternatives, RISC-V enables developers to create domain-specific processors for their systems-on-chip (SoCs). Custom instructions can boost throughput, reduce energy consumption, and shrink silicon area, all while preserving software compatibility and ecosystem portability. RISC-V’s open nature also reduces vendor lock-in, enabling faster innovation across automotive, AI, security, and high-performance computing (HPC).
Frequently asked questions about CPU IP cores
What is 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)?
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP) is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.