Discover CPU and Microcontroller IP for embedded processing, real-time control, and general-purpose computation in semiconductor designs. This category includes processor IP used in SoCs, ASICs, and embedded platforms requiring software programmability, deterministic control, and scalable compute performance.
Compare CPU and Microcontroller IP by ISA, bit width, safety support, performance level, memory architecture, debug features, ecosystem maturity, and target applications. These IP cores are widely used in automotive, industrial, IoT, consumer, and communication chips.
64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
AndesCore™ AX46MP(V) 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeS…
32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeSt…
32-bit Multiprocessors with Level-2 Cache-Coherence
AndesCore™ A45MP 32-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture.
The MIPS® M8500 real-time compute subsystem is a turnkey enabler for physical AI platforms that need precise control.
Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
configurable HW PQC acceleration with RISC-V processor for full CPU offload, configurable as Subsystem or RoT, with SCA and FIA p…
The 32-bit D45-SE is an 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level f…
The ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
The ARC-V™ RMX-500 Processors are based on the RISC-V instruction set architecture (ISA) and optimized for use in embedded applic…
ARC-V RMX Series Functional Safety Processor IP
The ARC-V™ RMX-110-FS and RMX-510-FS Functional Safety Processors simplify development of safety-critical applications and accele…
Centralised Real Time Processor IP Core
We provide many configurations for our cryptographic solutions based on the requirements of the project.
32-bit CPU IP core - ISO 26262 Automotive Functional Safety Compliant
AndesCore™ D25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications.
A CPU Foundation for the Automotive Industry The Arm Neoverse V3AE CPU is built to deliver maximum performance for automotive app…
Neoverse Compute Subsystems N3 (CSS N3)
The Performance-per-Watt Arm Neoverse N3 Platform Validated by Arm for Networking and Edge Markets configurable to target 5G, DPU…
Neoverse Compute Subsystems V3 (CSS V3)
The High-Performance Arm V3 Platform Performance-Optimized and Validated by Arm Arm Neoverse CSS V3 is the fastest path to buildi…
Synopsys ARC Functional Safety (FS) Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive …
64-bit RISC-V high-performance embedded core
64-bit RISC-V high-performance embedded core.
32-bit RISC-V compact high-performance embedded core
32-bit RISC-V compact high-performance embedded core.
64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems
64-bit RISC-V core with in-order dual issue pipeline based complex.
The Arm Cortex-M52 processor is the most area and energy efficient implementation of the Armv8.1-M architecture with Arm Helium v…
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on An…