Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
PQShield
Category:
CPU
Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
configurable HW PQC acceleration with RISC-V processor for full CPU offload, configurable as Subsystem or RoT, with SCA and FIA p…
Overview
Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload, configurable as Subsystem or RoT, with SCA and FIA protection
Engineered for crypto and implementation agility, PQPlatform-TrustSys is optimized for PQ/T hybrid secure boot and features industry-leading protections against power, EM, and fault-injection attacks.
Design Space
PQPlatform-TrustSys scales from a fully autonomous cryptographic hardware subsystem, to a fully-updatable Root of Trust, integrating advanced PQC algorithms alongside traditional standards (ECC, RSA) – fully supporting PQ/T hybrid deployments and legacy compatibility during transition periods. The system includes high-performance accelerators for bulk encryption, hashing, and symmetric cryptography, with seamless support for third-party integration.
Block Diagram
PQPlatform-TrustSys block diagram
Benefits
- Industry-leading support for PQC algorithms
- Best-in-class secure and efficient
countermeasures against DPA and DFA - Accelerated time-to-market
- Support for CAVP/CMVP and SESIP Compliance
Paths - Support for ECC/RSA, enabling hybrid and legacy
protocols during PQC transition - Advanced accelerators for symmetric cryptography
including AES, SHA-2, SHA-3, HMAC and other bulk
operations - Integration with third-party OTP, PUF and entropy
source components with prevalidated support
from PQShield
Applications
- Device identification and attestation
- Device provisioning
- Secure boot
- Secure firmware update
- Secure product configuration management
- Key storage and management
- Secure debug
- User authentication/authorization
- User data confidentiality and integrity protection
- Cryptographic primitives acceleration
Specifications
Identity
Part Number
PQPlatform-TrustSys
Vendor
PQShield
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United Kingdom
Learn more about CPU IP core
Announcing Arm AGI CPU: The silicon foundation for the agentic AI cloud era
For the first time in our more than 35-year history, Arm is delivering its own silicon products – extending the Arm Neoverse platform beyond IP and Arm Compute Subsystems (CSS) to give customers greater choice in how they deploy Arm compute – from building custom silicon to integrating platform-level solutions or deploying Arm-designed processors.
ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
The ChiPy DSL is Quadric's Python framework for building complete on-chip pipelines. Using YOLOX-M as a case study, we show how backbone inference, box decoding, and NMS run entirely on the Chimera GPNPU — no host CPU intervention, no DDR round-trips, just Python compiled to silicon.
Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster
As part of the new Arm Lumex compute subsystem (CSS) platform, the Arm C1 CPU cluster – the first built on the Armv9.3 architecture – is the next evolution of our highest performing CPU cluster for consumer devices, designed to unleash the full potential of on-device AI and elevate the user experience.
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and is demonstrated on different CPU designs.
Introducing Cortex-A320: Ultra-efficient Armv9 CPU Optimized for IoT
Unlock ultra-efficient performance, advanced AI processing, and robust security with the Cortex-A320—designed to power the future of IoT and edge AI innovation.
Frequently asked questions about CPU IP cores
What is Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload?
Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload is a CPU IP core from PQShield listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.