The ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
- RISC-V
CPU IP cores provide general-purpose processing for application, control, and system software workloads in modern SoC and ASIC designs.
These IP cores deliver programmable compute for embedded and high-performance SoCs, often serving as the central control or application processor in the architecture
This catalog allows you to compare CPU IP cores from leading vendors based on performance, power efficiency, software ecosystem, and process node compatibility.
Whether you are designing application processors, embedded systems, networking equipment, or compute SoCs, you can find the right CPU IP for your application.
The ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
The ARC-V™ RMX-500 Processors are based on the RISC-V instruction set architecture (ISA) and optimized for use in embedded applic…
High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
RiVAI-R1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V CPU core IP that supports the RV32IMFAC instruc…
32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue
With extreme low area, N100 is a 32b RISC-V processor designed specifically for low power application.
Our Processor for high embedded performance with RISC-V instruction-set compatibility, permit users to grasp the rich ecosystem o…
Compact High-Speed 32-bit CPU for Real-time and Linux Applications
AndesCore™ A25 is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of …
Compact High-Speed 64-bit CPU for Real-time and Linux Applications
AndesCore™ AX25 is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is ta…
The SiFive® Performance™ P570 Gen 3 brings fully out-of-order support coupled with support for the most comprehensive set of RVA2…
32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU).
32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue
N200 Series is designed for deeply embedded application with low power and area consumption.
RVA23, Multi-cluster, Hypervisor and Android
AndesCore™ AX66 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on An…
32-bit Multiprocessors with Level-2 Cache-Coherence
AndesCore™ A45MP 32-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture.
The ARC-V™ RPX-100 series processors feature a dual-issue, 64-bit superscalar architecture for use in high performance applicatio…
The ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-tim…
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on An…
The highest performance RISC-V core is ideal for consumer applications or used in conjunction with a vector processor in the data…
The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with…
64-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ AX45MP 64-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture.
32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU).
64-bit CPU Core with Level-2 Cache Controller
The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instruct…