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Vendor:
Nuclei System Technology
Category:
CPU
32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue
N200 Series is designed for deeply embedded application with low power and area consumption.
Overview
N200 Series is designed for deeply embedded application with low power and area consumption.
Key features
- Support RV32I/EMACB/Zc ISA.
- 2-stage pipeline, optimized micro-archtecture for power, area & cost efficiency.
- Support fast interrupt tail-chaining mechanism, vectored interrupt processing
mode for extremely fast interrupt response, and interrupt preemptions based
on interrupt levels. - Configurable ILM (Instruction Local Memory) and
DLM (Data Local Memory) with ECC - Configurable Instruction-Cache
- Support NICE.
- Full Standard Debug Function with JTAG/cJTAG port.
- Full Standard RISC-V Toolchain, and Linux/Windows IDE supported
Block Diagram
200 Series block diagram
Benefits
- Low Power
- RV32I/EMACB/Zc
- 2-Stage Pipeline
- Machine, User, Supervisor-Mode
- Security(PMP, TEE)
- AHB-Lite
- RISC-V Standard Debug
- JTAG & cJTAG
- Low Latency Interrupt
- Full Development Toolkit
Specifications
Identity
Part Number
200 Series
Vendor
Nuclei System Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
China
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Frequently asked questions about CPU IP cores
What is 32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue?
32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue is a CPU IP core from Nuclei System Technology listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.