Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
CPU
Compact High-Speed 64-bit CPU for Real-time and Linux Applications
AndesCore™ AX25 is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is ta…
Overview
AndesCore™ AX25 is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs to access address space over 4GB. AX25 also supports the RISC-V P-extension (draft) DSP/SIMD ISA contributed by Andes, single- and double-precision floating point and bit-manipulation instructions, and MMU for Linux based applications. AX25 comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, ECC for L1 memory soft error protection, and Andes Custom Extension™ (ACE) to add proprietary instructions to accelerate performance/power consumption critical spots.
AX25’s 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap™ and WFI mode for low power and power management, and JTAG debug interface for development support.
AndeStar™ V5 Architecture
| Key Features | Benefits |
|---|---|
| RISC-V RV64IMACFDBP instructions |
|
| 64-bit CPU architecture | Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs |
| RISC-V P-extension (draft) DSP/SIMD instructions with versatile operations | Boost the performance of voice, audio, image and signal processing |
| RISC-V single and double precision floating point instruction | Accelerate the processing of high precision arithmetic |
| RISC-V bit-manipulation instructions, including the Zba, Zbb, Zbc and Zbs extensions | Benefits codes with bit-wise operations |
| Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
| Andes Custom Extension™ (ACE) option to create customized instructions for software acceleration |
|
| 16/32-bit mixable instruction format | For compact code density |
| 32 general-purpose registers | For better code size and performance |
| Machine (M), User (U) and Supervisor (S) Privilege levels | For Linux and advanced operating systems with protection between kernel and user programs |
CPU Core
| Key Features | Benefits |
|---|---|
| 3.55 Coremark/MHz, 2.14 DMIPS/MHz* | Superior performance-per-MHz |
| 5-stage pipeline, with a full-cycle reserved for critical SRAM accesses | Superior performance-efficiency, while allowing for high speeds |
|
Extensive branch prediction features
|
|
|
Memory Management Unit
|
|
| Physical Memory Protection (PMP), 16 regions | Basic read/write/execute memory protection with minimum cost |
| Performance monitors | Program code performance tuning |
| StackSafe™ hardware stack protection |
|
|
Multiplier options
|
Option to choose between speed and area according to application's requirements |
| PowerBrake technology | Performance throttling to digitally reduce power consumption |
| QuickNap™ technology | Fast power-down/wake-up support for caches |
* AndeSight v500, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
| Key Features | Benefits |
|---|---|
|
I-Cache & D-Cache
|
|
|
ILM & DLM
|
|
| Soft-error protection: ECC or parity for I-Cache and D-Cache, ILM and DLM with SRAM interface | Code and data integrity protection |
| Bus manager port: AHB or AXI with 64-bit data, 32 to 64-bit address, AXI with I/D separate or joint bus | User-selectable bus interface for optimal efficiency |
| Bus subordinate port: AHB with 64-bit data, for ILM/DLM accesses | Efficient data transfer between CPU and SoC managers |
| Core/bus clock ratio of N:1 | Simplified SoC integration |
Platform-Level Interrupt Controller (PLIC)
| Key Features | Benefits |
|---|---|
|
Implements RISC-V PLIC specification
|
Allow individual interrupts to be serviced and prioritized without sharing |
|
Enhanced interrupt features
|
|
Debug Support
| Key Features | Benefits |
|---|---|
| Implements RISC-V debug specifications | Supported by industry debug tool suppliers |
| JTAG Debug Port | Industry-standard support |
| Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
| Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
Performance
| Core, Process | AX25 (w/o DSP, FPU), 28HPC+ | AX25 (with DSP, FPU), 28HPC+ |
|---|---|---|
| Frequency (MHz) | 1000 | 1000 |
| Dynamic power (uW/MHz) | 20 | 22 |
| Area (mm2) | 0.111 | 0.209 |
* Configured with cache and MMU. SVT 9-track library, SS corner, 0.81V, -40°C, and with I/O constraint. Power consumption at TT corner, 0.9V, 25°C
Key features
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- DSP/SIMD ISA to boost the performance of digital signal processing
- Floating point extension
- Bit-manipulation extensions
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
- 16/32-bit mixable instruction format for compacting code density
- Branch prediction to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU) and Physical Memory Protection (PMP)
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
Block Diagram
AndesCore™ AX25 block diagram
Benefits
- Performance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extension
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
- 16/32-bit mixable instruction format for compacting code density
- Branch predication to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU) and Physical Memory Protection (PMP)
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
- Flexibility
- Easy arrangement of preemptive interrupts
- StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
- ECC or Parity check on level-one memories for fault protection
- Several configurations to tradeoff between core size and performance requirements
- Power Management
- PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions
Applications
- Video processing
- Smart wireless switch/router
- Computer Vision and Pattern Recognition
- Machine/Deep Learning acceleration
What’s Included?
- AX25 with AE350 Platform
- Pre-integrated AX25, PLIC, Debug Module, plus AXI/AHB Platform
Specifications
Identity
Part Number
AndesCore™ AX25
Vendor
Andes Technology Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
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