Overview
The highest performance RISC-V core is ideal for consumer applications or used in conjunction with a vector processor in the datacenter. The P870 sets an impressive, new RISC-V performance bar across instruction availability, throughput, parallelism and memory bandwidth.
Bringing a 50% peak single thread performance upgrade (specINT2k6) over the previous generation Performance processors, the P870 is a six-wide, out-of-order core, meeting RVA 23, with a shared cluster cache enabling up to a 32-core cluster. High execution throughput comes with more instruction sets per cycle, more ALU and more branch units.
The P870A is designed for Automotive applications. For more information contact your sales representative.
Learn more about CPU IP core
SiFive is evolving the building blocks of RISC-V-based IP that are reimagining and democratizing every computing platform. We take a closer look at the new Performance P570 Gen 3 and its next-gen applications.
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For years, SiFive has been delivering a range of security capabilities that are optimized for deployment throughout the system, tightly coupled to products from its broad portfolio of processors. Building on the prior blogs that centered on performance and effective coupling of accelerators, I wanted to focus this blog on security and its role in the growing popularity of the SiFive Intelligence X100 product family.
In this blog, I dive a little deeper into the options to efficiently couple a processor from the X100 series to a hardware accelerator.
When I joined SiFive in early 2024, the initial focus (which has since broadened) was to explore how best to drive adoption of SiFive’s RISC-V technology into system-on-chip components targeting data center use cases.
Reflecting on how far we’ve come since SiFive launched the world’s first RISC-V development boards back in 2016, it’s clear we’ve been on an incredible journey together with the RISC-V software community.