Embedded Systems: Programmable Logic -> Reusable models trim software costs
Embedded Systems: Programmable Logic -> Reusable models trim software costs
Vendor:
So-Logic
Category:
Control Logic
Weighted majority voting combination rule core with parallel operation
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classificat…
Overview
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classification of the instance based on the classifications supplied by the ensemble members. Ensemble members whose classifications are being combined can be of any type, decision trees, neural networks, support vector machines, or some other predictive models. Even more, the ensemble can be even composed from a mixture of different predictive models.
So_ip_ecr_mvt_p core should be used in conjunction with some ensemble evaluation module that is able to calculate the instance classifications for all ensemble members in parallel. Using these classifications, so_ip_ecr_mvt_p core can calculate the combined classification of the current instance in parallel, to achieve the fastest classification speed.
So_ip_ecr_mvt_p core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_ecr_mvt_p design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_ecr_mvt_p core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
So_ip_ecr_mvt_p core should be used in conjunction with some ensemble evaluation module that is able to calculate the instance classifications for all ensemble members in parallel. Using these classifications, so_ip_ecr_mvt_p core can calculate the combined classification of the current instance in parallel, to achieve the fastest classification speed.
So_ip_ecr_mvt_p core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_ecr_mvt_p design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_ecr_mvt_p core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
Key features
- Implements Weighted Majority Voting combination rule that can be used to combine the classifications of individual ensemble members into one, collective classification
- Combination of individual members classifications is done in parallel, resulting in fast classification speed
- Ensemble members can be of any type, for example decision trees, neural networks, support vector machines, etc.
- Ensemble can be composed from a mixture of different predictive models
- No special IP blocks are needed to implement the core, only memory, adders and multipliers
What’s Included?
- VHDL Source Code or netlis
- Verification environment with regression suite
- Technical documentation
- Installation notes
- User Manual
- Datasheet
- Instantiation templates
- Reference Design
- Technical Support
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support
Specifications
Identity
Part Number
so_ip_ecr_mvt_p
Vendor
So-Logic
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Austria
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Frequently asked questions about Control Logic Accelerator IP cores
What is Weighted majority voting combination rule core with parallel operation?
Weighted majority voting combination rule core with parallel operation is a Control Logic IP core from So-Logic listed on Semi IP Hub.
How should engineers evaluate this Control Logic?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Control Logic IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.