Vendor: Cadence Design Systems, Inc. Category: Custom

Simulation VIP for AMBA CHI-C2C

Best-in-class Arm® AMBA® CHI-C2C Verification IP (VIP) for your IP, SoC, and System-level Design Testing Cadence provides a matur…

Verification IP View all specifications

Overview

Best-in-class Arm® AMBA® CHI-C2C Verification IP (VIP) for your IP, SoC, and System-level Design Testing

Cadence provides a mature and comprehensive Verification IP (VIP) for the Coherent Hub Interface Chip-to-Chip (CHI-C2C) specification, which is part of the Arm AMBA family of protocols. Incorporating the latest protocol updates, the Cadence Verification IP for CHI-C2C provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model. Designed for easy integration in testbenches at IP, systems with multiple CPUs, accelerators, or other device chiplets, the VIP for CHI-C2C provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms. Cadence provides an integrated solution for interconnect verification, which supports the verification of multi-chip symmetric multiprocessor (SMP) and multi-chip coherent accelerator attach. The VIP runs on all major simulators and supports SystemVerilog and e verification languages, along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Key features

  • Support C2C driving and monitoring
  • UCIe connectivity
  • Format X packetization
  • ReqS/ReqL DataS/DataL Resp/Resp2 WrReqDataS/WrReqDataL, Snoop and MiscU message types
  • Multi-container messaging
  • Credit support in MiscU/protocol-header message (no data credit pool)
  • Dvm connect/link activation/system coherency initialization flows
  • Property exchange

Block Diagram

Simulation VIP for AMBA CHI-C2C block diagram

Benefits

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Includes embedded cache model in RN-F models
  • Packet tracker for ease of debugging
  • Seamless integration with System Verification Scoreboard (SVD) and System Performance Analyzer (SPA)

Specifications

Identity

Part Number
Simulation VIP for AMBA CHI-C2C
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

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Provider

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Frequently asked questions about Custom Die-to-Die IP cores

What is Simulation VIP for AMBA CHI-C2C?

Simulation VIP for AMBA CHI-C2C is a Custom IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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