Vendor: Cadence Design Systems, Inc. Category: Custom

Simulation VIP for AMBA CHI-C2C

Best-in-class Arm® AMBA® CHI-C2C Verification IP (VIP) for your IP, SoC, and System-level Design Testing Cadence provides a matur…

Contact Provider Request Datasheet
Verification IP View all specifications

Overview

Best-in-class Arm® AMBA® CHI-C2C Verification IP (VIP) for your IP, SoC, and System-level Design Testing

Cadence provides a mature and comprehensive Verification IP (VIP) for the Coherent Hub Interface Chip-to-Chip (CHI-C2C) specification, which is part of the Arm AMBA family of protocols. Incorporating the latest protocol updates, the Cadence Verification IP for CHI-C2C provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model. Designed for easy integration in testbenches at IP, systems with multiple CPUs, accelerators, or other device chiplets, the VIP for CHI-C2C provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms. Cadence provides an integrated solution for interconnect verification, which supports the verification of multi-chip symmetric multiprocessor (SMP) and multi-chip coherent accelerator attach. The VIP runs on all major simulators and supports SystemVerilog and e verification languages, along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Key features

  • Support C2C driving and monitoring
  • UCIe connectivity
  • Format X packetization
  • ReqS/ReqL DataS/DataL Resp/Resp2 WrReqDataS/WrReqDataL, Snoop and MiscU message types
  • Multi-container messaging
  • Credit support in MiscU/protocol-header message (no data credit pool)
  • Dvm connect/link activation/system coherency initialization flows
  • Property exchange

Block Diagram

Simulation VIP for AMBA CHI-C2C block diagram

Benefits

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Includes embedded cache model in RN-F models
  • Packet tracker for ease of debugging
  • Seamless integration with System Verification Scoreboard (SVD) and System Performance Analyzer (SPA)

Specifications

Identity

Part Number
Simulation VIP for AMBA CHI-C2C
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about Custom IP core

How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes

This post opens a four-part series exploring how the expanded Cadence–TSMC collaboration helps accelerate AI silicon design innovation. It frames the collaboration at advanced-node design to reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs—accelerating time to silicon with greater confidence.

Reimagining Chip Design - From Spec to Signoff with Cadence AI Super Agents

At CadenceLIVE Silicon Valley 2026, Cadence took a major step toward fully autonomous chip design—introducing two powerful new AI Super Agents that complete an end-to-end chip design flow. The ViraStack AI Super Agent targets analog design and verification, while the InnoStack AI Super Agent addresses digital implementation and signoff.

Serial Wire Debug (SWD) Protocol: Efficient Debug Interface for Arm-Based System

The Serial Wire Debug (SWD) protocol is a compact, two-pin debug interface designed for Arm processor-based systems. As an alternative to the traditional JTAG interface, SWD provides efficient access to debug and trace features while minimizing pin count—a critical requirement for resource-constrained embedded and mobile devices.

Heterogeneous Multicore using Cadence IP

This blog presents a heterogeneous multicore system built with the RISC-V Host CPU and Cadence IP: Xtensa DSPs, and the Janus Network-on-Chip (NoC). While this example uses an RISC-V CPU, any other ISA with similar capabilities can also serve as the host CPU.

Frequently asked questions about Custom Die-to-Die IP cores

What is Simulation VIP for AMBA CHI-C2C?

Simulation VIP for AMBA CHI-C2C is a Custom IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP