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Vendor:
Agnisys, Inc.
Category:
Bus Fabric
Bus Bridges
Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely a…
Overview
Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely and without loss of data. SOC is essentially a system made up of components and their interconnections. Recently, the development of SOC chips with reusable IP cores has received more attention due to their lower cost and shorter time to market. The communication between the several IP cores should be lossless and designer-friendly.
Key features
- Supported Buses
- AXI4 Lite to APB
- Features
- Independent read and write channels
- Synchronous or asynchronous reset type
- Data Latency or wait stages
- AHB3 full / lite to APB / AXI4 lite
- Features
- Burst transfers
- Single clock-edge operation
- Non-tristate implementation
- Synchronous or asynchronous reset type
- Data Latency or wait stages
- Tilelink 1.8 to APB
- Features
- Independent read and write channels
- Synchronous or asynchronous reset type
- Data Latency or wait stages
Specifications
Identity
Part Number
Bus Bridges
Vendor
Agnisys, Inc.
Type
Silicon IP
Provider
HQ:
USA
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Frequently asked questions about On-Chip Bus IP cores
What is Bus Bridges?
Bus Bridges is a Bus Fabric IP core from Agnisys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Bus Fabric?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.