Vendor: LeWiz Communications, Inc. Category: Bus Fabric

AXI4 Memory Controller IP Core

ASIC and SoC designs require on-chip memory for on-chip program and data storage to gain high performance and low power advantages.

Controller View all specifications

Overview

ASIC and SoC designs require on-chip memory for on-chip program and data storage to gain high performance and low power advantages. To reduce risks, chip designs are usually emulated in FPGA hardware for thorough testing before taping out. Thus, on-chip memories use FPGA-like RAMs which are later replaced with silicon process’ RAMs. LeWiz’s AXI4 Memory Controller IP core enables the customer to emulate in FPGA and move ASIC designs to the silicon process seamlessly – 1 code flow from simulation, emulation to ASIC tape out; reducing risk of human errors.

Advanced eXtensible Interface 4 (AXI4) is widely used with on-chip modules. It allows for ease of integration, greater bandwidth with large data transfers (bursts) and parallel read/write accesses - supporting true dual-port RAM (TDPRAM). LeWiz IP core uses AXI4 bus for interfacing to customer’s internal bus. It can be used with RAMs generated from the RAM compilers which may be available from the foundries or other providers. Applications for LeWiz AXI4 Memory Controller range from microcontroller designs, to DSP chips, to integrated SoCs for high performance systems and others.

The design of the AXI4 Memory Controller is tuned for low latency, simultaneous reads/writes, efficient bus cycle, burst accesses, and fast data transmission through bidirectional data transfers. It supports memory-mapped addressing – simple and efficient decoding.

Key features

  • Well known AXI4 protocol interface 
  • Simultaneous read/write accesses 
  • Supports burst data transmissions 
  • FIXED, INCR, WRAP burst modes 
  • Supports narrow-lane, unaligned, unaligned narrow-burst transfers 
  • Optimize for high performance, low power 
  • Can specify ID, Address, Data Bus width + TDPRAM depth 
  • Automatic AXI4 controller data width matches TDPRAM 
  • Automatic corresponding AWSIZE/ARSIZE value to bus width 

Block Diagram

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Benefits

  • High Performance On-Chip Memory 
  • Supports FIXED, INCR, and WRAP bursts 
  • Simultaneous Read/Write 
  • Optimize for throughput 
  • For program execution, data storage 
  • Memory-mapped addresses
     

Specifications

Identity

Part Number
AXI4_controller
Vendor
LeWiz Communications, Inc.
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

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Provider

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Frequently asked questions about On-Chip Bus IP cores

What is AXI4 Memory Controller IP Core?

AXI4 Memory Controller IP Core is a Bus Fabric IP core from LeWiz Communications, Inc. listed on Semi IP Hub.

How should engineers evaluate this Bus Fabric?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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