Verification IP for AMBA AHB
Synopsys Verification IP (VIP) for Arm® AMBA® AHB™ provides a comprehensive set of protocol, methodology, verification, and produ…
Overview
Synopsys Verification IP (VIP) for Arm® AMBA® AHB™ provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA based designs supporting AHB5, AHB3, AHB2, AHB-Lite, and AHB Multi Layer.
Key features
- Complete protocol support for AHB5, AHB3, AHB2, AHB-Lite, and AHB Multi Layer
- Includes primary, secondary, monitor
- Configurable bus model
- Backdoor access to AHB secondary memory
- Ability to control wait states and secondary response types
- Ability to control signal values during idle periods
Block Diagram
Benefits
- Native SystemVerilog/Verilog with UVM
- Optional source code Test suite (EA)
- Runs on all major simulators
- Performance metrics for latency and throughput
- Reference Verification Platform
- Built-in port and system level checks for protocol, data integrity
- Built-in verification plan and coverage
- Verdi® protocol aware debug
- Debug port for transaction tracking on waveforms
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about On-Chip Bus IP cores
What is Verification IP for AMBA AHB?
Verification IP for AMBA AHB is a Bus Fabric IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Bus Fabric?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.