UMC L28HLP 28nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- UMC
- 28nm
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
UMC L28HLP 28nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HLP 28nm Clock Generator PLL - 220MHz-1100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HLP 28nm Clock Generator PLL - 440MHz-2200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPM 28nm Clock Generator PLL - 175MHz-875MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPM 28nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPM 28nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
The logiCLK is a programmable clock generator logicBRICKS IP core with twelve independent and fully configurable clock outputs.
0.8 to 25 MHz Intermediate-frequency amplifier
IFA consists of 4-stage amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digi…
4-bit programmable ECL LF divider (1…15 dividing ratio )
The 4-bit programmable ECL low-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which…
9-bit programmable ECL HF divider
The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 whic…
14-bit 8-channel 15 to 25 MSPS pipeline ADC
A block is a pipelined 8-channels ADC, built on a 12 1.5-bit multiplying DAC with sample data storage device and the final block …
AGDA21 is a 10bit 150MSPS current steering D/A converter.
AGDA11 is a 10bit current steering D/A converter.
AGAD12 is a 10bit 167MSPS Pipeline A/D converter.
BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.08-1.98V)
The SGC21412 is a versatile and scalable Power Controller for SoC integration.
Charge pump (CP) is a switched current sources controlled by phase-frequency detector which injects or removes some charge to inc…
Charge pump (CP) is a switched current sources controlled by phase-frequency detector which injects or removes some charge to inc…
Phase-frequency detector in CMOS logic
The phase-frequency detector (PFD) consists of a signal level converter from differential reduced swing ECL to single-ended full …
Phase-frequency detector in ECL logic
The phase-frequency detector (PFD) consists of 2 D-trigger with reset from external circuit, performed in ECL logic and multiplex…
1220 to 1610 MHz Image-rejection mixer
The mixer intended to perform a simultaneous RF signal carry, down conversion and image rejection.