Vendor: SiliconGate Category: Power On Reset (POR)

BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.08-1.98V)

The SGC21412 is a versatile and scalable Power Controller for SoC integration.

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Overview

The SGC21412 is a versatile and scalable Power Controller for SoC integration. When used standalone acts as a robust POR with monitoring functions. When part of a PMU (Power Management Unit) acts as the backbone. On a PMU it provides all the essential support functions, such as high PSRR voltage and current references, Under Voltge Lock Out (UVLO), start-up sequencing, Power On Reset (POR) and Power On Controller (POC). It can monitor multiple regulated voltages and generate the reset signals accordingly. The internal references have digital trimming bits for fine-tuning the performance or yield. The SGC21412 does not require any external decoupling capacitor or pin and achieves better than 1 % voltage reference accuracy over temperature. It operates from Tj = –40 °C to +125 °C.

Key features

  • Advanced Power Controller w/ POR
  • Large input voltage range: 1.08 - 1.98 V
  • Low IQ: 11 μA
  • Power-On-Reset
  • External voltage detector w/ UVLO
  • Reference voltage with 1 decoupled output
  • Bias current with 1 output
  • Level shifter disable signal generator
  • Support for voltage regulator bypass
  • Power-up sequencing controller

Block Diagram

SGC21412_R28HPCP block diagram

Benefits

  • The DB-I2C-S I2C Slave Controller IP Core targets embedded applications where the I2C Slave Controller connects to a bank of registers with SCL as the only clock, for low power, low noise applications.

What’s Included?

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Specifications

Identity

Part Number
SGC21412_R28HPCP
Vendor
SiliconGate
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SiliconGate
HQ: Portugal
Contact SiliconGate

Learn more about Power On Reset (POR) IP core

Method for Booting ARM Based Multi-Core SoCs

In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.

Analysis of RDC Paths for a million gate SoC

Reset is necessary to initialize the system and reach to a known state. Just like multiple clocks are required in an SoC to sustain various use models and performance, multiple resets are designed to cater different functional requirements. With this advent we also invite some issues due to crossings among different reset domains. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will become asynchronous crossing path and can cause metastability at destination register.

The silicon enigma: Bridging the gap between simulation and silicon

VLSI design teams are eagerly anticipating the full functional fab out Silicon to portray their months of hard work, on the other hand the Test teams are busy planning their functional coverage (to fill in the gaps of scan (atpg) patterns coverage holes) but more often than not, the unexpected happens and the teams are busy debugging the Si bring up for functional cases. This paper is trying to highlight the seemingly innocuous issues that occur on first few day of Si bring up and proactive steps that would help reduce these cycle.

BIST Verification at SoC level

With the increase complexity of modern day SoCs, the number of memory blocks and LBIST partitions are increasing, which is in turn making the verification efforts quite challenging. This paper highlights the key points to keep in mind while deciding the verification strategy for self-test, and what are the road-blocks in executing this “ideal” verification plan.

High Density - Low power Flip-Flop

In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult.

Frequently asked questions about Power-On Reset (POR) IP cores

What is BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.08-1.98V)?

BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.08-1.98V) is a Power On Reset (POR) IP core from SiliconGate listed on Semi IP Hub.

How should engineers evaluate this Power On Reset (POR)?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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