What is 9-bit programmable ECL HF divider?
9-bit programmable ECL HF divider is a Clock Generator IP core from NTLab listed on Semi IP Hub.
Vendor:
NTLab
Category:
Clock Generator
9-bit programmable ECL HF divider
The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 whic…
Overview
The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which is able to scale the structure either into minimum dividing ratio decreasing or maximum dividing ratio increasing. The differential circuit has higher noise immunity.
The block is fabricated on AMS BiCMOS 0.35 µm technology.
Key features
- AMS BiCMOS 0.35 µm
- Differential structure
- Dividing ratio is regulated in the range of 8...511 with step 1
- Input differential signal frequency up to 1.7 GHz
- Scalable structure
- Portable to other technologies (upon request)
Block Diagram
350AMS_NDIV_03 block diagram
Applications
- PLL frequency synthesizer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Specifications
Identity
Part Number
350AMS_NDIV_03
Vendor
NTLab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
Frequently asked questions about Clock Generator IP cores
How should engineers evaluate this Clock Generator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.