10G/25G/40G/100Gbit/s Ethernet MAC/PCS

Smooth integration of TCP/IP and UDP/IP protocols in your FPGA

The 10/25/40/100G MAC IP core is a Low-Latency Ethernet MAC with a latency of 44.8ns in 2749 LUTs for 10Gbit/s and 20.5ns in 2680 LUTs for 25Gbit/s. When combined with the  Low-Latency 10/25GPCS, the full packet round trip time for 10Gbit/s is ( MAC Input -> Wire -> MAC Output )  153.8ns in 5153 LUTs; 25Gbit/s ( MAC Input -> Wire -> MAC Output ) is 128ns in 7930 LUTs.

The IEEE 802.3by compliant 10/25/40/100G MAC/PCS was designed in house at Chevin Technology, to provide an easy path to the integration of protocols such as TCP/IP and UDP protocols in your FPGA, whilst using minimal FPGA resources. The 10/25/40/100G MAC simplifies the synthesis of ultra-fast Duplex 25Gbit/s Ethernet for FPGAs.

Chevin Technology offer a detailed user guide, expert support and design services to assist in the implementation of 10/25/40/100Gbit/s Ethernet connectivity in Intel® Agilex™ and AMD/Xilinx Virtex® UltraScale™ FPGAs. A reference design is available for technology partner Bittware’s IA-840F and IA-420F boards, as well as Alpha Data’s ADM-PCIE-8V3, ADM-PCE-9V3 boards. The 10/25/40/100G MAC/PCS is also compatible with AMD/Xilinx’s VCU108 board and has been tested with the Mellanox MCX4121A-ACAT NIC. Flexible licensing terms are available with Chevin Technology IP cores, to allow for the unique requirements of each customers’ project.

We understand that efficiency and reliability are crucial to our customers, and have created a powerful CRC32 checker & generator engine that checks the TX and RX data for errors, on a 64bit wide bus @ 390.625MHz.

Latency of the 10/25/40/100G MAC can be reduced even further by the use of Cut-through mode; the first byte appears only 8 nanoseconds after arriving at 25GMII. Alternatively, the Store-and-Forward mode reduces application workload, as the 25GMAC drops all corrupt frames. The Frame Checksum verifies frame integrity; the CRC32 check result is available 8 nanoseconds after the final byte is received.

The Deficit Idle Count optimizes the Inter Frame Gap (IFG) for absolute maximum Throughput and minimum Latency by maintaining an average IFG count.

• 10/25/40/100 Gbit Ethernet Connectivity in Intel and AMD/Xilinx FPGA
• Designed to IEEE 802.3by specification
• Low latency, TX 11ns, RX 8ns (Modes: cut-through/store-and-forward)
• Integrated FCS(CRC32) checker and generator
• Small Footprint, Virtex UltraScale 2680 LUTs / 2 Block RAMs
• Pause packet generate/accept
• Deficit Idle Control / Programmable IFG, less gaps, more throughput
• Store-and-forward /Cut-Through FIFO modes for minimum workload/latency
• Statistics counters, TX and RX traffic stats collected in size bins, frame type, FCS errors
• Local/Remote fault handling at RS Sub-Layer
• MAC Filter/Promiscuous Mode
• Easy to integrate, simple host interface to registers and statistics table.

Options

• AMD/Xilinx AXI4 streaming interface
• VLAN 802.1Q & PFC priority flow control
• IEEE 1588 Precision Time Protocol
• Advanced Hash Table based Filters, MAC address, IP, TCP/UDP port
• Encrypted Netlist

Lower Layer IP Blocks Network Side

• Connect to SFP28 (copper Direct Attach or optical Fibre) with Chevin Technology 25GPCS (PCS-PMA,25GBASE-R)
• Connect to back-plane

Upper Layers IP Blocks Application Side

• Add RTL-hardened functions for ICMP and ARP to any application using XGARP/ICMP

• Significantly increase the efficiency and rate of data transfer by providing lowest possible latency.
• Straightforward integration of 10Gbit/s Ethernet connectivity in Xilinx 7 Series, Kintex & Virtex® UltraScale™ FPGAs.
• Cut-through mode operation minimizes latency
• Store-and-forward feature allows for minimum application load
• Competitively priced licenses available to suit the size and requirements of each project.
• Customers can evaluate the RTT for themselves using a bitfile on Chevin Technology’s eco-system partner Alpha Data’s ADM-PCIE-KU3, ADM-PCIE-8V3, ADM-PCIE-9V3 boards.

• Trade execution & monitoring
• Data Storage & Capture systems
• HPC / Big Data systems
• Signal processing systems
• Data Mining

• Encrypted RTL/VHDL source code for simulation
• Encrypted compiled netlist
• Datasheet & User Guide to assist integration
• Simulation Test bench
• Build scripts for Vivado
• Support for integration into FPGA