ChipScope Pro IBERT for Virtex-7 GTX
The ChipScope™ Pro IBERT core for Virtex®-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Virt…
- Test / Debug
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
ChipScope Pro IBERT for Virtex-7 GTX
The ChipScope™ Pro IBERT core for Virtex®-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Virt…
ChipScope Pro IBERT for Kintex-7 GTX
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that…
AXI XADC IP provides the controller interface for System Monitor XADC hard macro on the Virtex®-7, Kintex™-7, Artix™-7 FPGA famil…
The AXI Quad Serial Peripheral Interface connects the AXI4 interface to those SPI slave devices which are supporting the Dual or …
The AMBA® ( Microcontroller Bus Architecture) AHB-Lite ( High Performance Bus) to AXI ( extensible interface) bridge translates A…
7 Series FPGA Transceivers Wizard
The LogiCORE™ IP 7 Series FPGAs Transceivers Wizard automates the task of creating HDL wrappers to configure Xilinx 7 Series FPGA…
SMIC 0.13µm 5V-3.3V 350mA Synchronous Buck DC-DC
The IP is a high efficiency, low ripple, current mode buck switching regulator with internal synchronous MOS switches, eliminatin…
SMIC 0.13um 12Bit 500Ksps R2R DAC
S13V33_R2RDAC_04 is a 12Bit 500Ksps DAC IP.
The Zaltys DVB-S2 Modulator (DVBS2-M) IP core is a variant of the Zaltys HDRM-M Modulator core which implements a DVB-S2 complian…
The Zaltys DVB-S2 Demodulator (DVBS2-D) IP core is a variant of the Zaltys HDRM-D2 demodulator core which implements a DVB-S2 com…
The Zaltys ISDBT-D IP core is a 3-layer ISDB-T hierarchical demodulator compatible with the ARIB STD-B31 standard for Terrestrial…
The Zaltys High Data Rate Modulator (HDRM-M) IP core efficiently realizes the digital baseband section of a high performance mode…
High Data Rate Enhanced Demodulator
The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …
The Dual HDLC controller provides two full-duplex HDLC channels, each with 512-byte data FIFO buffers for both directions.
Core implements the IPsec and SSL/TLS security standard at high data rates that require the cryptographic processing acceleration.
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design.
12-bit 50kS/s SAR-AD-Converter
IMST developed a discrete high resolution 14-bit Δ∑-ADC with a high output data IMST’s 12-bit analog-to-digital converter solutio…
Flash SPI controller master/slave
Veriest's SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses.
Remote Debug using Vivado Design Suite Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and prov…
The Processor Local Bus (PLB v4.6) to AMBA® ( Microcontroller Bus Architecture) eXtensible Interface (AXI) Bridge translates PLBV…