Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
- AV1 + 2
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
High Speed Access & Test IP USB Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle.
High Speed Access & Test IP PCIE Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle.
IEEE 802.15.4 Wireless Baseband IP
The LP-802.15.4 is a power and area-optimized implementation of the IEEE 802.15.4 physical and medium access control layers.
1G to 50G Single-Port MACsec Engine with TSN support
The MACsec-IP-161 is a versatile MACsec solution for silicon devices that require plug-and-play MACsec processing for an Ethernet…
The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.
CCSDS AR4JA LDPC Decoder & Encoder
The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding diff…
Fractional-N Frequency Synthesizer (40nm - 110nm)
The Fractional-N Frequency Synthesizers generate a stable clock from low frequency reference clock.
High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP)
The High Stability Oscillators generate 150MHz - 160MHz output frequency with an accuracy of +/-2% or +/-3% or +/-5%.
The Integer PLLs generate a stable clock from low frequency reference clock.
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP
The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interfa…
ultra Low power Bluetooth v5.3 Dual-Mode RF IP in TSMC40nm
Ultra-Low-Power Bluetooth Dual-Mode RF Transceiver IP in TSMC 40nm Logic LP processes node, The Radio Support standards like Blue…
H.264/AVC 4K 60p High Profile Decoder
- TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a efficient image compression method s…
H.264/AVC 4K 60p High Profile Encoder
- TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a efficient image compression method s…
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency …
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency …
H.265/HEVC H.264/AVC 422 12bit Multi-Codec for 8K
TMC’s HEVC/AVC Multi-Codec IP Core for 4K/8K are designed to be compliant with the H.264 4K (4096 x 2160) Video and H.265 8K (819…
CCSDS AR4JA LDPC Encoder/Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, …
LDPC corrects errors caused by flash storage failure mechanisms.
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.