Vendor: Techno Mathematical Co., Ltd. Category: Video Processing

JPEG Decoder 1-pixel/clock

Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP.

Overview

Since its standardization of ISO/IEC 10918-1 in 1994, JPEG has been continued to be used as a still image storage format.

TMC has developed and commercialized a baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP.

Specification

Compression Format JPEG (ISO/IEC 10918-1)
Throughput 1 pixel/clock @ YCbCr 4:2:2
Image Size 65k x 65x pixels (max.)
Image Format YCbCr 4:4:4/4:2:2/4:2:0/4:0:0
Bit Depth 8 bits
Interface Specification AXI3

This IP supports both color spaces of YCbCr and YUV.

Key features

  • By optimizing the encoding algorithm, TMC has achieved miniaturization and high speed.
  • Due to its compact design, this IP can be implemented in inexpensive FPGAs to reduce the costs. (Example: Cyclone IV series, Artix7 series)
  • Simple interface makes it easy to integrate and shortens the design time.

Block Diagram

Specifications

Identity

Part Number
TM20196
Vendor
Techno Mathematical Co., Ltd.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Video Processing IP core

Frequently asked questions about Video Processing IP

What is JPEG Decoder 1-pixel/clock?

JPEG Decoder 1-pixel/clock is a Video Processing IP core from Techno Mathematical Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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