High-Speed Test IO: Addressing High-Performance Data Transmission And Testing Needs For HPC & AI
Maximize limited package pins with IO that can act as high-speed test ports then be reused as low-power GPIOs during field operation.
Vendor:
Synopsys, Inc.
Category:
High-Speed
High Speed Access & Test IP PCIE Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle.
Overview
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle. Within the SiliconMAX Platform, High-Speed Access & Test (HSAT) IP plays a critical role enabling high-speed interfaces such as PCIe, typically already present in SoCs, to be re-used for high-bandwidth production test. Further, this opens up the possibility to reuse the same high speed test packets and to repeat manufacturing tests in-system or in-field, providing visibility of functional or performance degradation during the device’s lifetime. Manufacturing tests can be repeated in-system and/or in-field.
Key features
- PCIe functional protocol-based high-speed I/O for ATE, in-system & in-field
- Other interfaces (e.g. SPI) for in-system/in-field available
- Configurable Arm® AMBA® AXI slave interface to HSIO
- Configurable scan chains (512 max) and TAP supported
- Full RTL configuration and integration flow or Synopsys TestMAX Manager
- Arm AMBA AXI testbench generation
- Bypass mode allows scan chains to connect to HS Access & Test IP or GPIO pins
- Multiple levels of loop back for link validation
Benefits
- Easily repeat manufacturing tests in-system and in-field
- Reduce test time by eliminating the constraint of GPIO test pin data rate
- Re-use functional HSIO ports (PCIe and USB) for test and other data
- Avoid the need for large numbers of GPIO test pins
- High speed access to PVT & functional monitors and other sensor data
- Bandwidth scales with each new generation of PCIe
Applications
- High speed access to DFT & Silicon monitoring network through entire Silicon Lifecycle
What’s Included?
- Datasheet
- Configured RTL file
- Testbench with loop back tests
- Timing constraints
- Cdc constraints
- Synthesis constraint
Specifications
Identity
Part Number
dwc_hsa_pcie
Vendor
Synopsys, Inc.
Type
Silicon IP
Provider
HQ:
USA
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Frequently asked questions about High-Speed I/O Pad IP
What is High Speed Access & Test IP PCIE Version?
High Speed Access & Test IP PCIE Version is a High-Speed IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this High-Speed?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.