Vendor: Techno Mathematical Co., Ltd. Category: Video Processing

JPEG Encoder 1-pixel/clock

- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency …

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Overview

- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1

- High speed processing with low clock frequency

- Suitable for digital still camera .printer,facsimile and surveillance camera system

- 3 types of IPs are available.
Pixel/clock@4:2:2: 1, Performance (4K2K-fps@100MHz) 12.5 fps
Pixel/clock@4:2:2: 4, Performance (4K2K-fps@100MHz) 50 fps
Pixel/clock@4:2:2: 8, Performance (4K2K-fps@100MHz) 100 fps

Key features

  • - Image Format: Frame sequential method
  • - Input/Output Format: YUV 4:4:4/4:2:2/4:2:0/4:0:0
  • - Data bus protcol: AXI
  • - CPU bus protcol: AHB
  • - Error detection during decoding illegal stream
  • - Tables
    • (encode) Quantization table:2(Programmable)
      • Huffman table :4(*Programmable)
      • *:option only of 1pixle/clock
    • (decode) Quantization table:4
      • Huffman table :4
    • - Scaling function of Quantization table
    • - SOI,DHT,DQT,DRI,SOF0,SOS,RSTm,EOI

Benefits

  • TMC's DMNA (Digital Media New Algorithm), our original mathematical algorithm, drastically reduces the total amounts of calculations & operations, and realizes high-speed processing, high-quality image output, and low power consumption.

Applications

  • #NAME?

What’s Included?

  • Encrypted RTL
  • Datasheets
  • Verification environment
  • Synthesis constraint
  • Bit accurate model

Specifications

Identity

Part Number
TM20195
Vendor
Techno Mathematical Co., Ltd.
Type
Silicon IP

Provider

Contact Techno Mathematical Co., Ltd.

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is JPEG Encoder 1-pixel/clock?

JPEG Encoder 1-pixel/clock is a Video Processing IP core from Techno Mathematical Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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