For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
- NPU
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
Securyzr™ neo Core Platform is Secure-IC’s enhanced version of its flagship offering Securyzr™ integrated Secure Element (iSE) Se…
50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
PCIe PHY and controller solution
Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance.
Fault Tolerant DDR2/DDR3/DDR4 Memory controller
FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
GF 22FDX 5.5V OTP Auto-Grade1 IO Staggered
Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs.
Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs.
I²S Controller is designed to transfer audio data to and from Audio codec.
Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device.
The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one o…
Specifications: UAL_200 1.0 Interfaces: 802.3 dj compliant, UPLI DUT Types/Topology: Protocol TL Phy DL Reconciliation Sub Layer…
2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation.
1.22V/1uA Reference voltage and current source
180XFAB_RS_01 consists of a bandgap reference voltage regulator, formed temperature and power supply variations independent volta…
The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion…
SD4.x UHSII is PHY IP solution for UHS-II interface for next generation of ultra high speed used in both SDHC and SDXC.
Ethernet Switch VLAN 5x100M
Ethernet Switch/Router L2/L3/MPLS 12x10G
This L3 Ethernet Switch/Router IP core is built around a shared buffer memory architecture providing wire-speed switching and rou…