Vendor: NTLab Category: PLL

50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL

055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.

SMIC 55nm LL Silicon Proven View all specifications

Overview

055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz. It consists of the ring VCO with frequency from 400 to 800MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency. LO output signal is CMOS compatible.

Silicon area: 0.018 mm2.

ELECTRICAL CHARACTERISTICS

Parameter	Symbol	Condition	Value			Unit
Parameter	Symbol	Condition	min	typ.	max	Unit
Supply voltage	V_VCC12	-	1.08	1.2	1.32	V
Temperature range	T_j	-	-40	25	125	ºС
VCO control voltage	V_ctrl	-	0.1	-	1.05	V
Current consumption	I_VCC12	Fout = 400MHz	-	190	250	uA
Current consumption	I_VCC12	Fout = 800MHz	-	335	470	uA
Reference current	I_{ref_1uA}	-	-	1	-	uA
Current consumption in standby mode	I_stb	-	-	0.04	11.5	uA
Reference signal logic-level high	V_RefH	CMOS	0.8*VVCC12	-	VVCC12	V
Reference signal logic-level low	V_RefL	CMOS	0	-	0.2	V
Input logic-level high	V_{IH_VCC12}	For digitalinputs	0.8*V_VCC12	-	V_VCC12	V
Input logic-level low	V_{IL_VCC12}	For digitalinputs	0	-	0.2	V
Output logic-level high	V_{OH_VCC12}	For digital outputs	0.8*V_VCC12	-	V_VCC12	V
Output logic-level low	V_{OL_VCC12}	For digital outputs	0	-	0.2	V
VCO frequency	F_VCO	-	400	-	800	MHz
Output frequency	F_LO	-	50	-	800	MHz
LO duty cycle	DC_LO	-	40	50	60	%
Phase noise	PN_LO	F_LO = 400MHz at 1MHz	-	-96.2	-	dBc/Hz
Phase noise	PN_LO	F_LO = 800MHz at 1MHz	-	-92.5	-	dBc/Hz
Reference frequency	F_ref	-	4	6	20	MHz
Reference clock duty cycle	DC_ref	-	40	50	60	%
Comparison frequency	F_comp	-	4	-	20	MHz
Lock time	T_lock	-	-	9	14	us
Lock detector accuracy	S_err	-	15	20	27	ns
Lock monitoring period	MP	T_comp = 1/F_comp	-	32*T_comp	-	us

Block Diagram

055SMIC_PLL_01 block diagram

Silicon Options

Foundry	Node	Process	Maturity
SMIC	55nm	LL	Silicon Proven

Specifications

Identity

Part Number

055SMIC_PLL_01

Vendor

NTLab

Type

Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab

HQ: Lithuania

Frequently asked questions about PLL IP cores

What is 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL?

50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for smic Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.