The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…
- Channel Coding
- In Production
- Immediate
- yes
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…
The BCH decoder has four main functional blocks along with memory blocks.
Networking SerDes IP, Silicon Proven in ST 28FDSOI
The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling…
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver.
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in ST 28FDSOI
The HDMI receiver PHY (Physical layer), a single-port IP core, complies with all the specifications of HDMI 1.4.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY provides a…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 130/110G
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY supports p…
32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU).
32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue
With extreme low area, N100 is a 32b RISC-V processor designed specifically for low power application.
Embedded Flash Protection with Hardware Root of Trust and Lite Crypto Engine
The Flash Protection Series is a suite of enhancements available for PUFcc and PUFrt, extending the Hardware Root of Trust to pro…
Real-Time Clock with APB Interface
The RTC-APB core implements a real-time clock (RTC) and calendar facility together with an alarm function.
MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY
MIPI DSI transmitter IP is used to connect to up to two displays using the MIPI DSI-1 protocol.
MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.
MIPI CSI-2 Receiver v1.1 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.
USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data c…
64-bit CPU Core with Level-2 Cache Controller
The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instruct…
Compact High-Speed 32-bit CPU Core with Level-2 Cache
The 32-bit A27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructi…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with P…
8-stage superscalar RISC-V processor
The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instruct…