This IP is a phase locked loop which base on TSMC 40nm.
- TSMC
- 40nm
- G
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This IP is a phase locked loop which base on TSMC 40nm.
The IP is a thermal sensor based on SMIC 110nm process.
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12GHz to 14GHz,64 sub-band VCO
The WEA1214OS45G is a monolithic microwave integrated circuit, 64 sub-band voltage controlled oscillator.
The WEA2244PD45G is a microwave signal envelope detector.
The WEA7186PD55S is a differential ended envelope detector.
2.9V Low – Dropout (LDO) Voltage Regulator
The WEA3629LD45G is a high voltage ultra-low power Regulator designed for 5G mobile phones.
1.5V Low – Dropout (LDO) Voltage Regulator
The WEA3615LD45G is a voltage feedback amplifier (series – shunt) which active part is comprised of a telescopic cascode amplifie…
1V Low – Dropout (LDO) Voltage Regulator
The WEA3610LD45G is a voltage feedback amplifier (series – shunt) which active part is comprised of a telescopic cascode amplifie…
1.5V Bandgap Voltage Reference
The WEA15BG45G consists of the bandgap core with switching mode which produces a constant current Iconst and a constant voltage V…
The WEA10AD45 is a high performance SOI analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rate…
The WEA130170P55S consists of four cascaded differential amplifying stages.
The WEA2630P45G is an integrated power amplifier designed for Microwave Backhaul,5G Communications and mm-Wave Wireless Phase Arr…
The WEA2630L45G is an integrated low-noise amplifier designed for Microwave Backhaul,5G Communications and mm-Wave Wireless Phase…
High-performance RF front-end module for 5G mobile terminals
The WEA2630FE45G is a high-performance RF front-end module designed for 5G mobile terminals.
The Secure Debug IP provides isolation between 2 domains.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
5.72 GHz to 15.04 GHz Low phase Noise Fractional-N Synthesizer
The WEA615S55S is a wide band fractional – N frequency synthesizer with on Chip doubler implemented in ST BiCMOS55 process.
The Ethernet MAC and PCS 10G/25G is a silicon agnostic implementation of the IEEE 802.3 standard.