1.8GHz SSCG PLL on TSMC 28nm HPC+
Process : TSMC 28nm HPM/HPC Available metallization technologies : 4X2Y2R
- TSMC
- 28nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1.8GHz SSCG PLL on TSMC 28nm HPC+
Process : TSMC 28nm HPM/HPC Available metallization technologies : 4X2Y2R
Versatile, Ultra-Low-Power DSP for Audio, Voice, Vision, and AI
Smallest, ultra-low-energy DSP for always-on sensor fusion, always-listening voice trigger, and Bluetooth/BLE codecs The Cadence®…
Customizable Video Input controller
CVI is a fully Customizable Video Input controller IP core.
5GHz Multiplying PLL on TSMC 28nm
Available metallization technologies : 4X2Y2R and 5X2Y2R
TMC’s FRUC (Frame Rate Up-Converter) for 4K RTL Core utilizes proprietary ”DMNA- MEMC” (Motion Estimation and Motion Compensation…
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp.
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp.
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp.
Silicon agnostic implementation of the structure agnostic mapping method described in the IEEE 1914.3 standard The Radio Over Eth…
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver
The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
1.7GHz Multiplying PLL on TSMC 28nm
Available metalization technologies: 4X2Y2R and 5X2Y2R
Silicon Proven 1G Ethernet PHY IP as Whitebox
1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…
Graphics Processor Overlay IP Core
The GPU_OVERLAY IP Core is a versatile on-screen display processor that allows high-quality anti-aliased bitmap graphics and text…
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of TSMC 40nm L…
MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 on Samsung 28nm FD-SOI
The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28n…
MIPI D-PHY Receiver for CSI-2 of TSMC 40nm LP
The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process.
Tensilica AI Max - NNA 110 Single Core
Single-core neural network accelerator offering from 0.5 to 4 TOPS Optimized for machine learning inference applications The Cade…
The Rambus HBM3E / HBM3 controller cores are designed for use in applications requiring high memory bandwidth and low latency inc…
The AES engine IP is a high-performance cryptographic engine operates in AES NIST Federal information processing standard FIPS-19…
The LDPC Error Correction Core (Alcyone) delivers industry- error correction performance to enable 2D/3D, SLC/MLC/TLC/QLC NAND Fl…