The NVMe controller core (Meissa) is compliant with NVM Express 1.4 specification (NVMe 2.0 Mandatory) and targeted for both ente…
- NVMe Controller
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The NVMe controller core (Meissa) is compliant with NVM Express 1.4 specification (NVMe 2.0 Mandatory) and targeted for both ente…
Silicon agnostic Ethernet MAC IP for 40G, 100G speeds Ethernet MAC 40G/100G IP is a solution that enables the host to communicate…
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
HDCP Encryption-Decryption Engine
The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption Decryption Engine IP core implements the H…
CCSDS turbo encoder with sync marker, pseudo randomiser and input memory
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder with sync marker, optional pseudo-randomiser a…
CCSDS turbo decoder with sync marker synchroniser, descrambler and input memory
This is a CCSDS compatible 16 state error control turbo decoder with optional synchronisation, optional descrambling and input me…
Always-on Voice Activity Detection interfacing with analog microphones.
The WT-a-HD.03 is a mixed analog/digital Virtual Component (ViC) containing a Voice Activity Detection (VAD) engine for ultra-low…
Capless low input voltage LDO in GF 22FDX
Capacitor-less low input voltage LDO regulator in GlobalFoundries 22FDX
24-bit Cap-less ADC 101 dB SNR low power and low latency 3 channels
The sADC101-SW3-LR.01 is a mixed (analog and digital) Virtual Component containing two mono ADCs, and additional functions offeri…
24-bit Cap-less ADC 106 dB SNR with ASRC and phase alignement 6 channels
The hexADC-uLP-SW1.01 is a mixed (analog and digital) Virtual Component containing six mono ADCs, and additional functions offeri…
GNSS (GPS, Galileo, GLONASS, Beidou3, QZSS, SBAS) Ultra-low power RF Receiver IP
This GNSS RF Receiver IP is silicon-proven in TSMC40nm ULP process node, offers comprehensive support for all current satellite-b…
8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA
The SiFive Performance P270 is an 8-stage, dual-issue, efficient in-order pipeline compatible with the RISC-V RV64GCV ISA.
The second generation SiFive® Intelligence™ X390 is an 8-stage dual issue, in-order, superscalar processor with dual vector proce…
DVB-S2X NarrowBand Demodulator & Decoder IP (Silicon Proven)
This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 supporting…
HDR ISP framework for multi-camera applications
Xylon offers a logicBRICKS IP suite for implementing High-Dynamic Range (HDR) Image Signal Processing (ISP) pipelines in embedded…
64-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ AX45MP 64-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture.
16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provid…
DVB-S2/DVB-S2X Demapper/LDPC/BCH Decoder
The LCD01D is a high speed decoder for the DVB-S2/DVB-S2X low density parity check (LDPC) and Bose, Chaudhuri and Hocquenghem (BC…
Over-voltage Protection Module to handle direct connection of voltage regulators to a 5V battery using standard 1.8V IO devices