IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
Renesas
Category:
MIPI PHY
MIPI D-PHY Receiver for CSI-2 of TSMC 40nm LP
The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process.
Overview
The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process.
Key features
- Renesas MIPI D-PHY Receiver can be used for analog Receiver of following interface.
- MIPI alliance Specification for D-PHY Version 2.1 15 December 2016.
- MIPI alliance Specification for Camera Serial Interface 2 (CSI-2) Version 2.0 7 Dec 2016.
- Technology is TSMC 40nm LP 1p8M (4x2y1z).
- Supply voltage can be applied 1.18V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 1.0Gbps at High-speed mode.
Block Diagram
MIPI_D-PHY CSI (TSMC40LP) block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | LP eFlash | — |
Specifications
Identity
Part Number
MIPI_D-PHY CSI (TSMC40LP)
Vendor
Renesas
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI D-PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Japan
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Frequently asked questions about MIPI PHY IP
What is MIPI D-PHY Receiver for CSI-2 of TSMC 40nm LP?
MIPI D-PHY Receiver for CSI-2 of TSMC 40nm LP is a MIPI PHY IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.