The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.
- I2C / I3C
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The CAN-XL Bus Controller Core performs serial communication as per CAN 2.0, CAN-FD & CAN-XL Specifications.
The CAN-SEC Acceleration Engine Core implements the CAN-XL Protocol (CiA 610-1), CAN-XL Addon Part 1-Simple/Extercontent Indicati…
CAN FD LIGHT BUS CONTROLLER IP
The Controller Area Network – Flexible Data-Light (CAN-FD Light) Controller IP implements the CAN FD-Light (CIA 604-1) protocol.
The SPMI Host and Device IP (Configurable Controller Cores) implements MIPI SPMI2.0 protocols.
High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
The HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD2…
Compatible with a wide range of industry standard quartz crystals operating in the fundamental mode from 8 to 100 MHz.
The MIPI C/D-PHY combo IP is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for …
The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples.
DVB Local Scrambling Algorithm Core
The Helion DVB LSA Scrambler and Descrambler cores implement the Local Scrambling Algorithm as specified to provide MPEG-2 Transp…
The Helion Fast AES XTS core implements the AES “XEX-based Tweaked Codebook with Ciphertext Stealing” cipher mode (abbreviated to…
The Helion 3GPP KASUMI cores perform the f8 confidentiality and f9 integrity algorithms required to provide data security within …
802.11i Wireless Security Cores
These high performance cores have been designed to provide hardware acceleration of the underlying 802.11 WPA security algorithms…
G.9961 AES-CCM Frame Encryption Core
G.hn is a standard for home networking over power, coaxial, or telephone cable, or a combination of the three.
Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and receptio…
LVDS Tunneling Protocol and Interface (LTPI) IP
LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 Specification to facilitate the tunneling …
GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs.
The 10GBASE-R PHY Intel® FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or…
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the 3D look-up table (LUT) Intel® FPGA IP provides an ef…