UCIe IP cores enable high-bandwidth die-to-die connectivity in advanced packaging and chiplet architectures in modern SoC and ASIC designs.
These IP cores support standardized die-to-die connectivity for chiplet-based architectures with high bandwidth and ecosystem interoperability, helping designers scale heterogeneous integration with better bandwidth density, packaging flexibility, and subsystem reuse
This catalog allows you to compare UCIe IP cores from leading vendors based on bandwidth, latency, power efficiency, and process node compatibility.
Whether you are designing chiplet SoCs, AI packages, data-center processors, or advanced packaging platforms, you can find the right UCIe IP for your application.
UCIe-S PHY for Standard Package (x32) in TSMC N3P, East/West Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
Universal Chiplet Interconnect Express (UCIe™) PHY and Controller
High-bandwidth, low-power and low-latency standardized die-to-die interconnect
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hypers…
SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…
SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universa…
UCIe Controller (CHI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
UCIe Controller (AXI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
Die-to-Die (D2D) Interface for Chiplet Application
Compliant with the UCIe Specification Revision 1.1
UCIe D2D Adapter & PHY Integrated IP
A UCIe solution ready to support any protocol layer The D2D Adapter for UCIe combined with the UCIe PHY from a UCIe solution read…
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCLe - Ensures reliable validation and efficient connectivity for chiplets
UCIe VIP is a solution for validating and ensuring compliance in multi-chip semiconductor systems.
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…
The UCIe Verification IP provides an effective & efficient way to verify the UCIe components of an IP or SoC.
The UCIe 2.0 Verification IP offers a streamlined and efficient solution for verifying UCIe components within an IP or SoC.
The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package.
UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …